The 10 nanometer (10 nm) node is the technology node following the 14 nm node, and 10 nm class means chips made using process technologies between 10 and 20 nanometers.
The original naming of this technology node as "11 nm" comes from the International Technology Roadmap for Semiconductors (ITRS). According to the 2007 edition of this roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm, although Intel's Architecture and Silicon Cadence Model places its 10 nm node closer to the year 2015. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, claimed in 2008 that Intel sees a 'clear way' towards the 10 nm node. At the 11 nm node in 2015, Intel expects to use a half-pitch of around 21 nm. Nvidia's chief scientist, William Dally, claims that they will also reach 11 nm semiconductors by 2015, a transition he claims will be facilitated principally through new electronic design automation tools. How the use of such design tools will help Nvidia overcome the physical limitations of CMOS technology and conventional lithography is unclear. This design rule is likely to be realized by multiple patterning, given the difficulty of implementing EUV lithography by 2015.
While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Reported estimates indicate that transistors at these dimensions are significantly affected by quantum tunnelling. As a result, non-silicon extensions of CMOS, using III-V materials or nanotubes/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.
Due to the extensive use of ultra-low-k dielectrics such as spin-on polymers or other porous materials, conventional lithography, etch, or even chemical-mechanical polishing processes are unlikely to be used because these materials contain a high density of voids or gaps. At scales of ~10 nm, quantum tunneling, especially through gaps, becomes a significant phenomenon. Controlling gaps on these scales by means of electromigration can produce interesting electrical properties themselves.
Quantum tunneling may not be a disadvantage when its effect on device behavior is fully understood and used in the design. Future transistors may have insulating channels. An electron wave function decays exponentially in a "classically forbidden" region at a rate that can be controlled by the gate voltage. Interference effects are also possible. Alternate option is in heavier mass semiconducting channels.
On November 15, 2012, Samsung Electronics unveiled a 64 gigabyte (GB) embedded multimedia card (eMMC) based on 10 nm class process technology.
On April 11, 2013, Samsung announced that it was mass-producing High-Performance 128-gigabit 3-bit Multi-level-cell NAND Flash Memory with a technology somewhere between 10 nm and 20 nm.
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