14 nanometer

From Wikipedia, the free encyclopedia
  (Redirected from 16 nanometer)
Jump to: navigation, search

The 14 nanometer (14 nm) semiconductor device fabrication node is the technology node following the 22 nm/(20 nm) node. The naming of this technology node as "14 nm" came from the International Technology Roadmap for Semiconductors (ITRS). By current estimates the 14 nm technology is projected to be reached by semiconductor companies in the 2014 timeframe.[1]

14 nm resolution is difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning will be required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick,[2] but can also go up to about 100 nm.[3] The damage sensitivity is expected to get worse as the low-k materials become more porous.

For comparison, the lattice constant, or distance between surface atoms, of unstrained silicon is 543 pm (0.543 nm). Thus fewer than thirty atoms would span the channel length, leading to substantial leakage.

Tela Innovations and Sequoia Design Systems have developed a methodology allowing double exposure for the 14 nm node.[4]

Samsung and Synopsys have also begun implementing double patterning in 22 nm and 16 nm design flows.[5]

Mentor Graphics reported taping out 16 nm test chips in 2010.[6]

On January 17, 2011, IBM announced that they are teaming up with ARM to develop 14 nm chip processing technology.[7]

On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the 14 nm manufacturing processes and leading-edge 300 mm wafers.[8] The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel has since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips.[9]

On May 17, 2011, Intel announced a roadmap for 2014 that includes 14 nm transistors for their Xeon, Core, and Atom product lines.[10]

Technology demos[edit]

In 2005, Toshiba demonstrated 15 nm gate length and 10 nm fin width using a sidewall spacer process.[11] It has been suggested that for the 16 nm node, a logic transistor would have a gate length of about 5 nm.[12]

In December 2007, Toshiba demonstrated a prototype memory unit that uses 15 nanometer thin lines.[13]

In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a 16 nm SRAM chip.[14]

In September 2011, Hynix announced the development of 15 nm NAND cells.[15]

In December 2012, Samsung Electronics taped out a 14 nm chip.[16]

In September 2013, Intel demonstrated an Ultrabook laptop that uses a 14 nm Broadwell CPU and Intel CEO Brian Krzanich said "[CPU] will be shipping by the end of this year."[17] However, shipment had been delayed further until Q4 2014.[18]

References[edit]

  1. ^ "Common Platform confirms 14 nm". bit-tech.net. 
  2. ^ Richard, O.; et al. (2007). "Sidewall damage in silica-based low-k material induced by different patterning plasma processes studied by energy filtered and analytical scanning TEM". Microelectronic Engineering 84 (3): 517–523. doi:10.1016/j.mee.2006.10.058. 
  3. ^ Gross, T.; et al. (2008). "Detection of nanoscale etch and ash damage to nanoporous methyl silsesquioxane using electrostatic force microscopy". Microelectronic Engineering 85 (2): 401–407. doi:10.1016/j.mee.2007.07.014. 
  4. ^ Axelrad, V.; et al. (2010). "16nm with 193nm immersion lithography and double exposure". Proc. SPIE 7641: 764109. doi:10.1117/12.846677. 
  5. ^ Noh, M-S.; et al. (2010). "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". Proc. SPIE 7640: 76400S. doi:10.1117/12.848194. 
  6. ^ "Mentor moves tools toward 16-nanometer". EETimes. August 23, 2010. 
  7. ^ "IBM and ARM to Collaborate on Advanced Semiconductor Technology for Mobile Electronics". IBM Press release. January 17, 2011. 
  8. ^ "Intel to build fab for 14-nm chips". EE Times. 
  9. ^ "Intel shelves cutting-edge Arizona chip factory". Reuters. January 14, 2014. 
  10. ^ "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". AnandTech. May 17, 2011. 
  11. ^ Kaneko, A; Yagashita, A; Yahashi, K; Kubota, T et al. (2005). "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension". IEEE International Electron Devices Meeting (IEDM 2005). pp. 844–847. doi:10.1109/IEDM.2005.1609488. 
  12. ^ "Intel scientists find wall for Moore's Law". ZDNet. December 1, 2003. 
  13. ^ "15 Nanometre Memory Tested". The Inquirer. 
  14. ^ "16nm SRAM produced – Taiwan Today". taiwantoday.tw. 
  15. ^ Hübler, Arved; et al. (2011). "Printed Paper Photovoltaic Cells". Advanced Energy Materials 1 (6): 1018–1022. doi:10.1002/aenm.201100394. 
  16. ^ "Samsung reveals its first 14nm FinFET test chip". Engadget. December 21, 2012. 
  17. ^ "Intel reveals 14nm PC, declares Moore's Law 'alive and well'". The Register. September 10, 2013. 
  18. ^ "Intel postpones Broadwell availability to 4Q14". Digitimes.com. Retrieved 2014-02-13. 


Preceded by
22 nm
CMOS manufacturing processes Succeeded by
10 nm