WDC 65816/65802

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W65C816S microprocessor in PDIP40 package.

The W65C816S (also 65C816 or 65816) is a 16-bit microprocessor (MPU) developed by the Western Design Center (WDC). The W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU. The 65 in the part's designation comes from its 65C02 compatibility mode, and the 816 signifies that the MPU has selectable 8– and 16–bit register sizes.

In addition to the availability of 16 bit registers, the W65C816S features extended memory addressing to 24-bits, supporting up to 16 megabytes of random access memory, an enhanced instruction set, and a 16 bit stack pointer, as well as several new electrical signals for improved system hardware management.

At reset, the W65C816S starts in "emulation mode," meaning it essentially behaves as a 65C02. Following reset, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software. However, unlike the PDIP40 version of the 65C02, which is a pin-compatible replacement for its NMOS ancestor, the PDIP40 W65C816S is not pin-compatible with a 65C02

Contents

History [edit]

Development of the W65C816S commenced in 1982 after Bill Mensch, founder and CEO of WDC, as well as the designer of the 65C02 microprocessor, consulted with Apple Computer on a new version of the Apple II series of personal computers that would, among other things, have improved graphics and sound. Apple wanted an MPU that would be software compatible with the 6502 then in use in the Apple II but with the ability to address more memory, and to load and store 16 bit words.

PLCC-44 version of W65C816S microprocessor, shown mounted on a single-board computer.

The result was the 65C816, finished in March 1984, with samples provided to both Apple and Atari. Apple subsequently integrated the 65C816 into the Apple IIGS computer. Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the chip's layout.

In the 1990s, the 65C816 (as well as its antecedent, the 65C02) was converted to a fully static core, which made it possible to completely stop the processor clock without losing data in any of the registers. This feature, along with the use of asynchronous static RAM, made it possible to produce designs that used minimal power when in a standby state.

The basic 65C816 design was second-sourced by GTE, Sanyo and others from the mid-to-late 1980s to the early 1990s. As of 2012, the W65C816S is available from WDC in a 40 pin PDIP or PLCC44 package, as well as a core for ASIC integration (for example Winbond's W55V9x series of TV Edutainment ICs). WDC, itself a fabless semiconductor company, works with various foundries to produce the W65C816S, as well as other compatible products. Discrete processors are available through a number of electronics distributors. For designers who wish to include W65C816S functionality into a custom ASIC, WDC offers RTL (register-transfer level) code in Verilog.

In the past, WDC offered a 65(C)02 PDIP40 pin-compatible variant of the W65C816S referred to as the 65C802. The 65C802 was fully compatible with the 65C02 in all respects, but could be made to behave as a 65C816 if desired (including the use of 16–bit registers, although addressing was still limited to the 65C02's 16-bits). The 65C802 was produced by WDC and GTE during the mid-to-late 1980s and early 1990s. Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production.

Features [edit]

  • Fully static CMOS design for low power consumption (300 µA at 1 MHz) and increased noise immunity.
  • Wide operating voltage range: 1.8 V ± 5%, 2.5 V ± 5%, 3.0 V ± 5%, 3.3 V ± 10%, 5.0 V ± 5% for use with varying voltage peripherals.
  • Wide operating frequency range.
  • Emulation mode allows complete software compatibility with the 65C02, excepting undocumented opcodes.
  • 24-bit memory addressing provides access to 16 MB of memory space.
  • 16-bit ALU, accumulator, stack pointer and index registers.
  • Valid Data Address (VDA) and Valid Program Address (VPA) outputs for dual cache and cycle steal DMA implementation.
  • Vector Pull (VPB) output to indicate when an interrupt vector is being addressed.
  • Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions, such as memory access violations.
  • Separate program and data bank registers allow program segmentation or 16 MB linear addressing (data only).
  • Direct register and stack relative addressing provides capability for reentrant, recursive and re-locatable programming.
  • 24 addressing modes—13 original 6502 modes with 92 instructions using 256 op codes, including most new opcodes implemented in the 65C02.
  • Block-move instructions, allowing rapid copying of data structures from one area of RAM to another with minimal code.
  • Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) instructions further reduce power consumption, decrease interrupt latency and allows synchronization with external events.
  • Co-Processor (COP) instruction with associated vector supports co-processor configurations, e.g., floating point processors
  • Reserved "escape" (WDM) instruction for future two-byte opcodes and a link to future designs. WDM is the initials of W65C816S designer William D. Mensch.

Notable applications [edit]

See also [edit]

References [edit]

  1. ^ The Unofficial CMD page
  • Eyes, David; Lichty, Ron (1986). Programming the 65816 including the 6502, 65C02, and 65802. New York: Brady Books/Prentice Hall Press (Simon & Schuster, Inc). ISBN 0-89303-789-3.
Ebook on WDC’s Documentation page: Assembly Language Programming Manual for the W65C02 and W65C816

External links [edit]

This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.

65xx-series CPUs from MOS Technology, second source/clone vendors, and the Western Design Center
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