ARM11

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ARM11 is an ARM architecture 32-bit RISC microprocessor family which introduced the ARMv6 architectural additions. These include SIMD media instructions, multiprocessor support and a new cache architecture. The implementation included significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10 families, and is used in smartphones from Apple, Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in late 2002.

The ARM11 family are currently the only ARMv6-architecture cores. There are however ARMv6-M cores (Cortex-M0 and Cortex-M1), addressing microcontroller applications; ARM11 cores target more demanding applications.

[edit] Differences from ARM9

In terms of instruction set, the ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.

Microarchitecture improvements in ARM11 cores^[1] include:

SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead
Unaligned and mixed-endian data access is supported
Reduced heat production and lower overheating risk
Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
- Longer: 8 (vs 5) stages
- Out-of-order completion
- Dynamic branch prediction/folding (like XScale)
- Cache misses don't block execution of non-dependent instructions
- Load/store parallelism
- ALU parallelism
64-bit data paths

JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.

Also of note was ARM's effort to promote good Verilog coding styles and techniques to ensure semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. This is because ARM cores are integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, so the impact of its register-transfer level (RTL) quality is magnified many times.^[2] Without such attention, integrating an ARM11 with third party designs could risk exposing hard-to-find latent bugs. (The ARM11 generation focused more heavily on synthesis than previous generations, making such concerns be more of an issue.)