ARM Cortex-A57

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ARM Cortex-A57
Designed by ARM
Instruction set ARMv8-A
Cores 1–4 per cluster, multiple clusters[1]
L1 cache 80 KiB (48 KiB I-cache with parity, 32 KB D-cache with ECC) per core
L2 cache 512 KiB to 2 MiB
L3 cache none

The ARM Cortex-A57 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline.[1] It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).

Overview[edit]

  • Pipelined processor with deeply out of order, speculative issue 3-way superscalar execution pipeline
  • DSP and NEON SIMD extensions are mandatory per core
  • VFPv4 Floating Point Unit onboard (per core)
  • Hardware virtualization support
  • Thumb-2 instruction set encoding reduces the size of 32-bit programs with little impact on performance.
  • TrustZone security extensions
  • Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
  • 32 KiB data + 48 KiB instruction L1 cache per core
  • Integrated low-latency level-2 cache controller, up to 2 MB per cluster

Chips[edit]

In January 2014 AMD announced the Opteron A1100. Intended for servers, the A1100 has 4 or 8 Cortex-A57 cores, support for up to 128 GiB of DDR3 or DDR4 RAM, an 8-lane PCIe controller, 8 SATA (6 Gbit/s) ports, and two 10GigE ports.[2]

In June 2014, T-Platforms in cooperation with Rostec and Rosnano announced Russian-made processors called "Baikal", 64-bit Cortex-A57 designs that run at 2 GHz.[3]

See also[edit]

References[edit]

External links[edit]