ARM Cortex-A7 MPCore

ARM Cortex-A7 MPCore

Designed by	ARM Holdings
Instruction set	ARMv7
Cores	1-4
L1 cache	8-64 KB/8-64 KB
L2 cache	Optional, up to 1 MB

The ARM Cortex-A7 MPCore is a processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture.

Overview

It has two target applications; firstly as a smaller, faster, and more power-efficient successor to the Cortex-A8. The other use is in the big.LITTLE architecture, combining one or more A7 cores with one or more Cortex-A15 cores into a heterogeneous system. To do this it is fully feature-compatible with the A15.

Key features of the Cortex-A7 core are:

• Partial dual-issue, in-order microarchitecture with an 8 stage pipeline
• NEON SIMD instruction set extension
• VFPv4 Floating Point Unit
• Thumb-2 instruction set encoding
• Jazelle RCT
• Hardware virtualization
• Large Page Address Extensions (LPAE)
• Integrated level 2 Cache (0-1 MB)
• 1.9 DMIPS / MHz

Chips

Several system-on-chips (SoC) have implemented the Cortex-A7 core, including:

• Allwinner A20 (dual core A7 + Mali-400 MP2 GPU)
• Allwinner A31s (quad core A7 + PowerVR SGX544MP2 GPU)
• Allwinner A31 (quad core A7 + PowerVR SGX544MP2 GPU)
• HiSilicon K3V3, big.LITTLE architecture with dual-core Cortex-A7 and dual-core Cortex-A15. Use ARM Mali-T658 GPU.
• Marvell PXA1088 (quad core A7)
• Mediatek MT6589 (quad core A7 + Imagination PowerVR SGX544 GPU)
• Qualcomm Snapdragon S4 Play MSM8226 and MSM8626 (quad core A7 + Adreno 305 GPU)

See also

• ARM architecture
• List of ARM microprocessor cores
• List of applications of ARM cores
• JTAG

External links

ARM Holdings

• Official website
• Cortex-A7 Technical Reference Manuals