ARM Cortex-M

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ARM Cortex-M0 and Cortex-M3 ICs from NXP and Energy Micro
Die of a STM32F100C4T6B ARM Cortex-M3 microcontroller with 16 KB flash memory, 24 MHz CPU, motor control, and CEC functions. Manufactured by STMicroelectronics.

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings. The cores are intended for microcontroller use, and consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, and Cortex-M4.[1][2][3][4][5]

Overview[edit]

Main article: ARM architecture
Announced
Year Core
2004 Cortex-M3
2007 Cortex-M1
2009 Cortex-M0
2010 Cortex-M4
2012 Cortex-M0+

ARM license[edit]

ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization[edit]

Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Some of the most important options for the Cortex-M cores are:

  • SysTick Timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.[6][7][8] Though the SysTick timer is optional, it's rare to see a Cortex-M microcontroller without it.
  • Bit Banding: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bitband region. This allows every individual bit in the bit-banding region to be directly accessible from a word-aligned address, and individual bits to be toggled from C/C++ without performing a read-modify-write sequence of instructions.[6][7][8]
  • Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions.[6][7][8]
ARM Cortex-M Optional Components[6][7]
ARM
Cortex-M
SysTick
Timer
Bit
Banding
Memory Protection
Unit (MPU)
Cortex-M0[1]
Optional
Optional[9]
No
Cortex-M0+[2]
Optional
Optional[9]
Optional
Cortex-M1[3]
Optional
No No
Cortex-M3[4]
Yes
Optional
Optional
Cortex-M4[5]
Yes
Optional
Optional
  • Note: Most Cortex-M3 and M4 chips have Bit-Banding and MPU. The Bit-Banding option can be added to the Cortex-M0 / M0+ using the Cortex-M System Design Kit.[9]
  • Note: Software should validate the existence of a feature before attempting to use it.[8]

Additional features[6][7]

  • External interrupts: 0 to 32
  • Wake-up interrupt controller: Optional
  • Vector Table Offset Register: Optional
  • Data endianness: Little-endian or big-endian
  • Instruction fetch width: 16-bit only, or mostly 32-bit
  • User/Privilege support: Optional
  • Reset all registers: Optional
  • Single-cycle I/O port: Optional
  • Debug Access Port (DAP): Optional
  • Halting debug support: Optional
  • Number of watchpoint comparators: 0 to 2
  • Number of breakpoint comparators: 0 to 4

Instruction sets[edit]

The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture,[6] the Cortex-M3 implements the ARMv7-M architecture,[7] and the Cortex-M4 implements the ARMv7E-M architecture.[7] The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / M0+ / M1 can execute without modification on the Cortex-M3 and Cortex-M4. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4.[6][7]

ARM Cortex-M instruction sets[6][7]
ARM
Cortex-M
Thumb Thumb-2 Hardware
multiply
Hardware
divide
Saturated
math
DSP
extensions
Floating-point ARM
architecture
Core
architecture
Cortex-M0[1]
Most
Subset
1 or 32 cycle
No No No No
ARMv6-M[6]
Von Neumann
Cortex-M0+[2]
Most
Subset
1 or 32 cycle
No No No No
ARMv6-M[6]
Von Neumann
Cortex-M1[3]
Most
Subset
3 or 33 cycle
No No No No
ARMv6-M[6]
Von Neumann
Cortex-M3[4]
Entire Entire 1 cycle Yes Yes No No
ARMv7-M[7]
Harvard
Cortex-M4[5]
Entire Entire 1 cycle Yes Yes Yes
Optional
ARMv7E-M[7]
Harvard
  • Note: The Cortex-M0 / M0+ / M1 doesn't include these Thumb instructions: CBZ, CBNZ, IT; nor does it include a divide instruction.[6][7]
  • Note: The Cortex-M0 / M0+ / M1 only include these Thumb-2 instructions: DMB, DSB, ISB, MRS, MSR.[6][7]
  • Note: If a smaller silicon die size is required, the Cortex-M0 / M0+ / M1 can implement a smaller and slower multiply instruction.

All four Cortex-M cores implement a common instruction subset that consists of: Thumb subset, Thumb-2 subset, and multiply. The Cortex-M0 / M0+ / M1 include all older Thumb instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).[6][7]

The Cortex-M0 / M0+ / M1 were designed to be the smallest size possible, thus having the fewest instructions of the Cortex-M family. The Cortex-M3 adds 3 Thumb instructions and all Thumb-2 instructions, plus a 10-12 cycle hardware divide and saturated math instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit.[6][7] If the Cortex-M4 has the floating point unit, then it is known as the Cortex-M4F.

ARM Cortex-M instructions
Instructions Instruction
size
Cortex
M0
Cortex
M0+
Cortex
M1
Cortex
M3
Cortex
M4
Cortex
M4F
ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STMIA, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD
16-bit
Yes Yes Yes Yes Yes Yes
BL, DMB, DSB, ISB, MRS, MSR
32-bit
Yes Yes Yes Yes Yes Yes
CBNZ, CBZ, IT
16-bit
No No No Yes Yes Yes
ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, CLZ, CMN, CMP, DBG, EOR, LDC, LDMA, LDMDB, LDR, LDRB, LDRBT, LDRD, LDREX, LDREXB, LDREXH, LDRH, LDRHT, LDRSB, LDRSBT, LDRSHT, LDRSH, LDRT, MCR, LSL, LSR, MLS, MCRR, MLA, MOV, MOVT, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SDIV, SEV, SMLAL, SMULL, SSAT, STC, STMDB, STR, STRB, STRBT, STRD, STREX, STREXB, STREXH, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UDIV, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD
32-bit
No No No Yes Yes Yes
PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16
32-bit
No No No No Yes Yes
VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUB
32-bit
No No No No No Yes

Cortex-M0[edit]

Cortex-M0
Instruction set Thumb subset,
Thumb-2 subset

The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.

Key features of the Cortex-M0 core are:[1]

  • ARMv6-M architecture[6]
  • Instruction sets
    • Thumb (most), missing CBZ, CBNZ, IT
    • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR
    • 32-bit hardware multiply, 1-cycle or 32-cycles (silicon option)
  • 3-stage pipeline
  • 13.36 µW/MHz dynamic power requirement

Chips[edit]

The following microcontrollers are based on the Cortex-M0 core:

The following chips have a Cortex-M0 as a secondary core:

Cortex-M0+[edit]

Cortex-M0+
Instruction set Thumb subset,
Thumb-2 subset
Freescale FRDM-KL25Z Board with KL25Z128VLK (Kinetis L series)

The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing one to use the same compiler and debug tools. The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the memory protection unit (MPU) and the vector table relocation.[2] Key features of the Cortex-M0+ core are: [2]

  • ARMv6-M architecture[6]
  • Instruction sets (same as Cortex-M0)
    • Thumb (most), missing CBZ, CBNZ, IT.
    • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR.
    • 32-bit hardware multiply, 1-cycle or 32-cycles (silicon option)
  • 2-stage pipeline (one less than Cortex-M0)
  • 11.21 µW/MHz dynamic power requirement
  • Silicon options:
    • Micro Trace Buffer (MTB) (unique to Cortex-M0+)
    • Single-cycle I/O port (unique to Cortex-M0+)
    • Vector table relocation (same as Cortex-M3 and Cortex-M4)
    • 8 region memory protection unit (MPU) (same as Cortex-M3 and Cortex-M4)

Chips[edit]

The following microcontrollers are based on the Cortex-M0+ core:

Cortex-M1[edit]

Cortex-M1
Instruction set Thumb subset,
Thumb-2 subset

The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips.

Key features of the Cortex-M1 core are:[3]

  • ARMv6-M architecture[6]
  • Instruction sets
    • Thumb (most), missing CBZ, CBNZ, IT.
    • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR.
    • 32-bit hardware multiply, 3-cycle or 33-cycles (silicon option)

Chips[edit]

The following FPGA vendors support the Cortex-M1 as soft-cores:

Cortex-M3[edit]

Cortex-M3
Instruction set Thumb, Thumb-2,
Saturated Math
NXP LPCXpresso Development Board with LPC1343
mbed Board with NXP LPC1768
The TI Ducati SIP core uses a Cortex-M3 cores to offload video acceleration and image processing.

Key features of the Cortex-M3 core are:[4][10]

  • ARMv7-M architecture[7]
  • Instruction sets
    • Thumb (entire)
    • Thumb-2 (entire)
    • 1-cycle 32-bit hardware multiply, 2-12 cycle 32-bit hardware divide, saturated math support
  • 3-stage pipeline with branch speculation
  • 1 to 240 physical interrupts, plus NMI
  • 12 cycle interrupt latency
  • Integrated sleep modes
  • 8 region memory protection unit (MPU) (silicon option)
  • 1.25 DMIPS/MHz
  • 90 nm implementation[11]
    • 32 µW/MHz
    • 0.12 mm2

Chips[edit]

The following microcontrollers are based on the Cortex-M3 core:

The following chips have a Cortex-M3 as a secondary core:

Cortex-M4[edit]

Cortex-M4(F)
Instruction set Thumb, Thumb-2,
Saturated Math, DSP,
FPU (Cortex-M4F only)
Energy Micro Wonder Gecko STK Board with EFM32WG990
TI Stellaris Launchpad Board with LM4F120

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP Instructions, and optional floating-point unit (FPU). If a core contains an FPU, it is known as a Cortex-M4F, otherwise it is a Cortex-M4. Key features of the Cortex-M4 core are:[5]

  • ARMv7E-M architecture[7]
  • Instruction sets
    • Thumb (entire)
    • Thumb-2 (entire)
    • 1-cycle 32-bit hardware multiply, 2-12 cycle 32-bit hardware divide, saturated math support
    • DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
    • Floating-point extension (silicon option): Single-precision floating point unit, IEEE-754 compliant. This is called the FPv4-SP extension.
  • 3-stage pipeline with branch speculation
  • 1 to 240 physical interrupts, plus NMI
  • 12 cycle interrupt latency
  • Integrated sleep modes
  • 8 region memory protection unit (MPU) (silicon option)
  • 1.25 DMIPS/MHz

Chips[edit]

The following microcontrollers are based on the Cortex-M4 core:

The following microcontrollers are based on the Cortex-M4F (M4 + FPU) core:

The following chips have either a Cortex-M4 or M4F as a secondary core:

Development tools[edit]

Segger J-Link EDU. ARM JTAG/SWD debug probe with USB interface to host. Low price model for educational and home users.

Documentation[edit]

The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer and documents from CPU core vendor (ARM Holdings).

A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufacturer datasheet for the exact physical chip, manufacturer detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes the instruction set(s).

Documentation tree (top to bottom)
  1. IC manufacturer website.
  2. IC manufacturer marketing slides.
  3. IC manufacturer datasheet.
  4. IC manufacturer reference manual.
  5. ARM core website.
  6. ARM core generic user guide.
  7. ARM core technical reference manual.
  8. ARM architecture reference manual.

IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External Links section for links to official ARM documents.

See also[edit]

References[edit]

Further reading[edit]

  • Digital Signal Processing and Applications Using the ARM Cortex M4; 1st Edition; Donald Reay; Wiley; 250 pages; 2014; ISBN 978-1118859049.
  • Assembly Language Programming : ARM Cortex-M3; 1st Edition; Vincent Mahout; Wiley-ISTE; 256 pages; 2012; ISBN 978-1848213296.
  • The Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors; 3rd Edition; Joseph Yiu; Newnes; 600 pages; 2013; ISBN 978-0124080829.
  • The Definitive Guide to the ARM Cortex-M0; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0-12-385477-3.

External links[edit]

ARM Cortex-M Official Documents
ARM
Core
ARM
Website
ARM Generic
User Guide
ARM Technical
Reference Manual
ARM Architecture
Reference Manual
Cortex-M0
Link
Link
Link
ARMv6-M
Cortex-M0+
Link
Link
Link
ARMv6-M
Cortex-M1
Link
Link
Link
ARMv6-M
Cortex-M3
Link
Link
Link
ARMv7-M
Cortex-M4
Link
Link
Link
ARMv7E-M
Quick Reference Cards
  • Instructions: Thumb (1), ARM and Thumb-2 (2), Vector Floating-Point (3), arm.com
  • Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives (5).
Migrating
Other