Advanced Vector Extensions
Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later on by AMD with the Bulldozer processor shipping in Q3 2011. AVX-512 expands AVX to 512-bit support utilizing a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing processor scheduled to ship in 2015.
AVX provides new features, new instructions and a new coding scheme.
- 1 New features
- 2 AVX-512
- 3 New coding scheme
- 4 Applications
- 5 Compiler and assembler support
- 6 Operating system support
- 7 CPUs with AVX
- 8 New 256-bit instructions
- 9 Advanced Vector Extensions 2
- 10 Advanced Vector Extensions 512
- 11 Future instruction sets
- 12 References
The width of the SIMD register file is increased from 128 bits to 256 bits, and renamed from XMM0–XMM7 to YMM0–YMM7 (in x86-64 mode, YMM0–YMM15). In processors with AVX support, the legacy SSE instructions (which previously operated on 128-bit XMM registers) now operate on the lower 128 bits of the YMM registers.
AVX introduces a three-operand SIMD instruction format, where the destination register is distinct from the two source operands. For example, an SSE instruction using the conventional two-operand form a := a + b can now use a non-destructive three-operand form c := a + b, preserving both source operands. AVX's three-operand format is limited to the instructions with SIMD operands (YMM), and does not include instructions with general purpose registers (e.g. EAX). Such support will first appear in AVX2.
AVX-512 expands AVX to 512-bit support utilizing a new EVEX prefix encoding. AVX-512 introduces 32 vector registers (ZMM) each 512 bits wide, eight dedicated mask registers, 512-bit operations on packed floating point data or packed integer data, embedded rounding controls (override global settings), embedded broadcast, embedded floating-point fault suppression, embedded memory fault suppression, new operations, additional gather/scatter support, high speed math instructions, compact representation of large displacement value, and the ability to have optional capabilities beyond the foundational capabilities. AVX-512 offers a level of compatibility with AVX that is stronger than prior transitions to new widths for SIMD operations. Unlike SSE and AVX that cannot be mixed without performance penalties, the mixing of AVX and AVX-512 instructions is supported without penalty. AVX registers YMM0–YMM15 map into the Intel AVX-512 registers ZMM0–ZMM15, very much like SSE registers map into AVX registers. Therefore, in processors with Intel AVX-512 support, SSE and AVX instructions operate on the lower 128 or 256 bits of the first 16 ZMM registers.
New coding scheme
The new VEX coding scheme introduces a new set of code prefixes that extends the opcode space, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits.
- Suitable for floating point-intensive calculations in multimedia, scientific and financial applications (integer operations are expected in later extensions).
- Increases parallelism and throughput in floating point SIMD calculations.
- Reduces register load due to the non-destructive instructions.
- Improves Linux RAID software performance 
Compiler and assembler support
Recent releases of GCC starting with version 4.6 (although there was a 4.3 branch with certain support) and the Intel Compiler Suite starting with version 11.1 support AVX. The Visual Studio 2010/2012 compiler supports AVX via intrinsic and /arch:AVX switch. The Open64 compiler version 4.5.1 supports AVX with -mavx flag. Absoft supports with -mavx flag. PathScale supports via the -mavx flag. The Vector Pascal compiler supports AVX via the -cpuAVX32 flag. The GNU Assembler (GAS) inline assembly functions support these instructions (accessible via GCC), as do Intel primitives and the Intel inline assembler (closely compatible to GAS, although more general in its handling of local references within inline code). Other assemblers such as MASM VS2010 version, YASM 0.7.0, FASM, NASM and JWASM also apparently support AVX instructions.
Operating system support
AVX adds new register-state through the 256-bit wide YMM register file, so explicit operating system support is required to properly save & restore AVX's new registers between context switches. The following operating system versions will support AVX:
- Apple OS X: Support for AVX added in 10.6.8 (Snow Leopard) update released on June 23, 2011.
- Linux: supported since kernel version 2.6.30, released on June 9, 2009.
- Windows: supported in Windows 7 SP1 and Windows Server 2008 R2 SP1, Windows 8
- Windows Server 2008 R2 SP1 with Hyper-V requires a hotfix to support AMD AVX (Opteron 6200 and 4200 series) processors, kb 2568088
- FreeBSD in a patch submitted on 21 January 2012, which was included in the 9.1 stable release
- DragonFly BSD added support in early 2013.
- Solaris 10 Update 10 and Solaris 11
CPUs with AVX
Issues regarding compatibility between future Intel and AMD processors are discussed under XOP instruction set.
New 256-bit instructions
These AVX instructions are in addition to the ones that are 256-bit extensions of the legacy 128-bit SSE instructions:
|VBROADCASTSS, VBROADCASTSD, VBROADCASTF128||Copy a 32-bit, 64-bit or 128-bit memory operand to all elements of a XMM or YMM vector register.|
|VINSERTF128||Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.|
|VEXTRACTF128||Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.|
|VMASKMOVPS, VMASKMOVPD||Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged.|
|VPERMILPS, VPERMILPD||Shuffle 32-bit or 64-bit vector elements, with a register or memory operand as selector.|
|VPERM2F128||Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.|
|VZEROALL||Set all YMM registers to zero and tag them as unused. Used when switching between 128-bit use and 256-bit use.|
|VZEROUPPER||Set the upper half of all YMM registers to zero. Used when switching between 128-bit use and 256-bit use.|
Advanced Vector Extensions 2
Advanced Vector Extensions 2 (AVX2), also known as Haswell New Instructions, is an expansion of the AVX instruction set introduced in Intel's Haswell microarchitecture. AVX2 makes the following additions:
- Expansion of most integer AVX instructions to 256 bits
- 3-operand general-purpose bit manipulation and multiply
- Gather support, enabling vector elements to be loaded from non-contiguous memory locations
- DWORD- and QWORD-granularity any-to-any permutes
- Vector shifts
- 3-operand fused multiply-accumulate support (FMA3)
CPUs with AVX2
Advanced Vector Extensions 512
CPUs with AVX-512
- Xeon Phi Knights Landing: AVX3.1 (AVX-512F foundation plus AVX-512 CDI, AVX-512 PFI and AVX-512 ERI) 2015.
- Future Intel Processors to be named later
- speculation: Skylake: AVX3.2 (AVX-512F foundation plus TBA) processor, 2016.
- speculation: Cannonlake (AVX-512 foundation plus TBA) processor, 2017.
Capabilities beyond AVX-512 foundation instructions
- AVX-512 Conflict Detection Instructions (CDI), Purpose: efficient conflict detection to allow more loops to be vectorized, Supported by: Knights Landing
- AVX-512 Exponential and Reciprocal Instructions (ERI), Purpose: exponential and reciprocal operations designed to help implement transcendental operations, Supported by: Knights Landing
- AVX-512 Prefetch Instructions (PFI), Purpose: new prefetch capabilities, Supported by: Knights Landing
Future instruction sets
The VEX coding scheme and EVEX coding scheme allows future extensions of operations.
Descriptions of other future x86 instruction sets:
- James Reinders (23 July 2013), AVX-512 Instructions, Intel, retrieved 20 August 2013
- Haswell New Instruction Descriptions Now Available, Software.intel.com, retrieved 2012-01-17
- "Linux RAID". LWN. 2013-02-17.
- YASM 0.7.0 Release Notes http://yasm.tortall.net/releases/Release0.7.0.html
- Twitter, retrieved 2010-06-23[unreliable source?]
- x86: add linux kernel support for YMM state, retrieved 2009-07-13
- Linux 2.6.30 - Linux Kernel Newbies, retrieved 2009-07-13
- Floating-Point Support for 64-Bit Drivers, retrieved 2009-12-06
- Add support for the extended FPU states on amd64, both for native 64bit and 32bit ABIs, svnweb.freebsd.org, 2012-01-21, retrieved 2012-01-22
- "FreeBSD 9.1-RELEASE Announcement". Retrieved 2013-05-20.
- "Intel Offers Peek at Nehalem and Larrabee". ExtremeTech. 2008-03-17.
- "Intel Core i7-3960X Processor Extreme Edition". Retrieved 2012-01-17).
- Dave Christie (2009-05-07), Striking a balance, AMD Developer blogs, retrieved 2012-01-17
- New "Bulldozer" and "Piledriver" Instructions, AMD, October 2012