|This article needs additional citations for verification. (December 2012)|
|Traded as||NASDAQ: ALTR
S&P 500 Component
|Headquarters||San Jose, California, U.S.|
|Key people||John P. Daane
(Chairman, President and CEO)
|Products||FPGAs, CPLDs, Embedded Processors, ASICs|
|Revenue||US$ 1.783 billion (2013)|
|Operating income||US$ 584.1 million (2013)|
|Net income||US$ 556.8 million (2013)|
|Total assets||US$ 4.658 billion (2013)|
|Total equity||US$ 3.333 billion (2013)|
|Employees||2,884 (December 2011)|
Altera Corporation is a Silicon Valley manufacturer of PLDs, reconfigurable complex digital circuits. The company released its first PLD in 1984. Altera's main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs (Complex programmable logic devices), the HardCopy series ASICs and Quartus II design software.
The Stratix series FPGAs are the company's largest, highest bandwidth devices, with up to 1.1 million logic elements, integrated transceivers at up to 28 Gbit/s, up to 1.6 Tbit/s of serial switching capability, up to 1,840 GMACs of signal-processing performance, and up to 7 x72 DDR3 memory interfaces at 800 MHz. Cyclone series FPGAs and SoC FPGAs are the company's lowest cost, lowest power FPGAs, with variants offering integrated transceivers up to 5 Gbit/s. In between these two device families are Arria series FPGAs and SoC FPGAs, which provide a balance of performance, power, and cost for mid-range applications such as remote radio heads, video conferencing equipment, and wireline access equipment. Arria FPGAs have integrated transceivers up to 10 Gbit/s.
In December 2012, the company announced that they are shipping their first 28 nm SoC FPGA devices. According to Altera, fully depleted silicon on insulator (FDSOI) chip manufacturing process is beneficial for FPGAs.
Altera offers a design flow based on HardCopy ASICs, which transitions the FPGA design, once finalized, to a form which is not alterable. This design flow reduces design security risks as well as costs for higher volume production. Design engineers can prototype their designs in Stratix series FPGAs, and then migrate these designs to HardCopy ASICs when they're ready for volume production.
The unique design flow makes hardware/software co-design and co-verification possible. The flow has been benchmarked to deliver systems to market 9 to 12 months faster, on average, than with standard-cell solutions. Design engineers can employ a single RTL, set of intellectual property (IP) cores, and Quartus II design software for both FPGA and ASIC implementations. Altera's HardCopy Design Center manages test insertion.
In May 2008, Altera introduced the industry's first 40-nm programmable logic devices: the Stratix IV FPGAs and HardCopy IV ASICs. Both devices are available with integrated transceiver options. Since then, the company has also introduced Stratix IV GT FPGAs, which have 11.3-Gbit/s transceivers for 40G/100G applications, and Arria II GX FPGAs, which have 3.75-Gbit/s transceivers for power- and cost-sensitive applications.
Semiconductors manufactured on a 40-nm process node address many of the industry's key challenges, including power consumption, device performance, and cost. Altera's devices are manufactured using techniques such as 193-nm immersion lithography and technologies such as extreme low-k dielectrics and strained silicon. These techniques and technologies bring enhancements to device performance and power efficiency.
In April 2010, Altera introduced the FPGA industry's second 28-nm device, the Stratix V FPGA (to Xilinx's Kintex-7 FPGA), available with transceivers at speeds up to 28 Gbit/s. This device family has more than 1 million logic elements, up to 53 Mb of embedded memory, up to 7 x72 DDR3 DIMMs at 800 MHz, 1.6-Gbit/s LVDS performance, and up to 3,680 variable-precision DSP blocks. In August 2011, Altera began shipping 28-nm Stratix V GT devices featuring 28-gigabits-per-second (Gbps) transceivers.
The devices also feature some unique features. Embedded HardCopy Blocks harden standard or logic-intensive applications, increasing integration and delivering twice the density without a cost or power penalty. Altera has developed a user friendly method for partial reconfiguration, so core functionality can be changed easily and on the fly. And there is a path to HardCopy V ASICs, when designs are ready for volume production. Also, Altera’s 28 nm FPGAs aim to reduce power requirements to 200 mW per channel.
In December 2012, the company announced the shipment of its first 28 nm Cyclone V SoC devices, which have a dual-core ARM Cortex-A9 processor system with FPGA logic on a single chip. The new SoCs are targeted for wireless communications, industrial, video surveillance, automotive and medical equipment markets. With these SoCs devices, users are able to create custom field-programmable SoC variants for power, board space, performance and cost optimization.
In February 2013, Altera announced an agreement with Intel to use Intel’s foundry services to produce its 14-nm node for the future manufacturing of its FPGAs, based on Intel’s 14 nm tri-gate transistor technology, in place of Altera’s ongoing agreement with Taiwan Semiconductor Manufacturing Corporation (TSMC).
Altera and its partners offer an array of intellectual property (IP) cores that serve as building blocks that design engineers can drop into their system designs to perform specific functions. IP cores eliminate some of the time-consuming tasks of creating every block in a design from scratch.
Altera offers an embedded portfolio with a broad selection of soft processor cores.
- Nios II embedded processor
- Freescale ColdFire v1 core (free for Cyclone III FPGA).
- ARM Cortex-M1 processor
And one hard IP processor core.
- ARM Cortex-A9 processor
All of Altera's devices are supported by a common design environment, Quartus II design software. Quartus II software is available in a subscription-based edition and a free Web-based edition. It includes a number of tools to foster productivity. Some Quartus II software features include:
- SOPC Builder, a tool in Quartus II software that eliminates manual system integration tasks by automatically generating interconnect logic and creating a testbench to verify functionality
- Qsys, a system-integration tool that is the next generation of SOPC Builder. It uses an FPGA-optimized network-on-chip architecture that doubles the fMAX performance vs. SOPC Builder.
- SoCEDS, a set of development tools, utility programs, run-time software, and application examples to help you develop software for SoC FPGA embedded systems.
- DSP Builder, a tool that creates a seamless bridge between the MATLAB/Simulink tool and Quartus II software, so FPGA designers have the algorithm development, simulation, and verification capabilities of MATLAB/Simulink system-level design tools
- External memory interface toolkit, which identifies calibration issues and measures the margins for each DQS signal.
- Generation of JAM/STAPL files for JTAG in-circuit device programmers.
On June 21, 2006, Altera Corp. restated its 1996-2005 financial results to correct accounting errors related to stock-based compensation expense.
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