Altera Hardware Description Language
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AHDL is a proprietary digital Hardware Description Language (HDL) from Altera Corporation for programming their Complex Programmable Logic Devices (CPLD) and Field Programmable Gate Arrays (FPGA). This language has an Ada programming language-like syntax and similar operation to VHDL or Verilog. It is supported by Altera's Quartus and Max+ series of compilers.
A disadvantage of AHDL is that it is proprietary. An advantage of AHDL is that all language constructs are synthesizable. AHDL is to Verilog much as assembly language is to a higher-level programming language: in AHDL, you have more control but less high-level support.
% a simple AHDL up counter, released to public domain 13 November 2006 % % [block quotations achieved with percent sign] % % like c, ahdl functions must be prototyped % % PROTOTYPE: FUNCTION COUNTER (CLK) RETURNS (CNTOUT[7..0]); % % function declaration, where inputs, outputs, and bidirectional pins are declared % % also like c, square brackets indicate an array % SUBDESIGN COUNTER ( CLK :INPUT; CNTOUT[7..0] :OUTPUT; ) % variables can be anything from flip-flops (as in this case), tri-state buffers, state machines, to user defined functions % VARIABLE TIMER[7..0]: DFF; % as with all hardware description languages, think of this less as an algorithm and more as wiring nodes together % BEGIN DEFAULTS TIMER.prn = VCC; % this takes care of d-ff resets % TIMER.clrn = VCC; END DEFAULTS; TIMER.d = TIMER.q + H"1"; END;
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