Amber (processor core)

From Wikipedia, the free encyclopedia
Jump to: navigation, search

The Amber processor core is an open-source ARM-compatible 32-bit RISC processor. It is hosted on the OpenCores website and is part of a movement to develop a library of open source hardware intellectual property.[1] The Amber core is fully compatible with the ARMv2 instruction set and is therefore supported by the GNU toolchain. This older version of the ARM instruction set is supported because it is not covered by patents so can be implemented without a license from ARM Holdings, unlike some previous open source projects.[2] The Amber project provides a complete embedded FPGA system incorporating the Amber core and a number of peripherals, including UARTs, timers and an Ethernet MAC.

There are two versions of the core provided in the Amber project. The Amber 23 has a 3-stage pipeline, a unified instruction and data cache, a Wishbone interface, and is capable of 0.75 DMIPS per MHz. The Amber 25 has a 5-stage pipeline, separate data and instruction caches, a Wishbone interface, and is capable of 1.0 DMIPS per MHz. Both cores implement exactly the same ISA and are 100% software compatible.

The Amber 23 core is a very small 32-bit core that provides good performance. Register-based instructions execute in a single cycle, except for instructions involving multiplication. Load and store instructions require three cycles. The core's pipeline is stalled either when a cache miss occurs, or when the core performs a wishbone access.

The Amber 25 core provides 30 to 40% better performance than the Amber 23 core but is also 30 to 40% larger. Register-based instructions execute in a single cycle, except for instructions involving multiplication, or complex shift operations. Load and store instructions also execute in a single cycle unless there is a register conflict with a following instruction. The core's pipeline is stalled when a cache miss occurs in either cache, when an instruction conflict is detected, when a complex shift is executed, or when the core performs a wishbone access.

Both cores have been verified by booting a Linux 2.4 kernel. Versions of the Linux kernel from the 2.4 branch and earlier contain configurations for the supported ISA. The 2.6 and later versions of the Linux kernel do not explicitly support the ARM v2a ISA and so requires more modifications to run. The cores do not contain a memory management unit (MMU) so they can only run the non-virtual memory variant of Linux, μClinux.

The cores were developed in Verilog 2001 and are optimized for FPGA synthesis. For example there is no reset logic, all registers are reset as part of FPGA initialization.

For a description of the ARMv2 ISA, see Archimedes Operating System - A Dabhand Guide,[3] or Acorn RISC Machine Family Data Manual.[4]

References[edit]

External links[edit]