Back end of line

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The back end of line (BEOL) is the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer.[1] BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.

After the last FEOL step, there is a wafer with isolated transistors (without any wires). In BEOL part of fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC process, more than 10 metal layers can be added in the BEOL.

The process used to form DRAM capacitors creates a rough and hilly surface, which makes it difficult to add metal interconnect layers and still maintain good yield. In 1998, state-of-the-art DRAM processes had 4 metal layers, while state-of-the-art logic processes had 7 metal layers. [2]

As of 2002, 5 or 6 layers of metal interconnect are common.[3]

As of 2009, typical DRAM devices (1 Gbit) use 3 layers of metal interconnect, tungsten on the first layer and aluminum on the higher layers.[4][5]

As of 2011, many gate arrays are available with a 3-layer interconnect.[6] Many power ICs and analog ICs use a 3-layer interconnect.[7]

The top-most layers of a chip have the thickest and widest and most widely-separated metal layers, which make the wires on those layers have the least resistance and smallest RC time delay, so they are used for power distribution and clock distribution. The bottom-most metal layers of the chip, closest to the transistors, have thin, narrow, tightly-packed wires, used only for local interconnect. Adding layers can potentially improve performance, but adding layers also reduces yield and increases manufacturing cost. [8]

All the chips decoded by the Visual6502 project have only one or two metal layers, including the RCA 1802, the 6800, the 6502, the 8086, the 6809, the 68000, etc.[9]

Chips with a single metal layer typically use the polysilicon layer to "jump across" when one signal needs to cross another signal -- such as the RCA CDP1802[10] and the 4004, giving effectively 2 layers of interconnections.[11]

Many microprocessors were designed with two metal interconnect layers, both of them aluminum, including the 1987 CVAX and the 1989 Rigel.

Many high-performance microprocessors were designed with 3 metal interconnect layers, all of them aluminum. Those included several processors using the CMOS-3 process, including the 1992 Alpha 21064; and processors using the CMOS-6 process, including the 1996 StrongARM.

The AMD Athlon Thunderbird has 6 interconnect layers, the AMD Athlon Palomino has 7 interconnect layers, the AMD Athlon Thoroughbred A has 8 interconnect layers, and the AMD Athlon Thoroughbred B has 9 interconnect layers.[12] The Intel Xeon Dunnington has nine copper interconnect layers.[13]

Steps of the BEOL:

  1. Silicidation of source and drain regions and the polysilicon region.
  2. Adding a dielectric (first, lower layer is Pre-Metal dielectric, PMD - to isolate metal from silicon and polysilicon), CMP processing it
  3. Make holes in PMD, make a contacts in them.
  4. Add metal layer 1
  5. Add a second dielectric (this time it is Intra-Metal dielectric)
  6. Make vias through dielectric to connect lower metal with higher metal. Vias filled by Metal CVD process.
    Repeat steps 4-6 to get all metal layers.
  7. Add final passivation layer to protect the microchip

Before 1998, practically all chips used aluminum for the metal interconnection layers. [14] The four metals with the highest electrical conductivity are silver with the highest conductivity, then copper, then gold, then aluminum.

As of 2011, many commercial processes support 2 or 3 metal layers; the most layers supported on a commercial process is 11 layers, and 12 layers are expected to be supported soon.[15]

After BEOL there is a "back-end process" (also called post-fab), which is done not in the cleanroom, often by a different company. It includes wafer test, wafer backgrinding, die separation, die tests, IC packaging and final test.

References[edit]

  1. ^ Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8. 
  2. ^ Yong-Bin Kim and Tom W. Chen. "Assessing Merged DRAM/Logic Technology". 1998. [1] [2]
  3. ^ M. Rencz. "Introduction to the IC technology". 2002. [3]
  4. ^ Bruce Jacob, Spencer Ng, David Wang. "Memory systems: cache, DRAM, disk". 2007. Section 8.10.2. "Comparison of DRAM-optimized process versus a logic-optimized process". Page 376. [4]
  5. ^ Young Choi. "Battle commences in 50nm DRAM arena". 2009. [5]
  6. ^ Epson Gate Arrays
  7. ^ Petrov group. "Intersil -- power management strategy". 2010. [6]
  8. ^ Paul DeMone. "The Incredible Shrinking CPU" 2004. [7]
  9. ^ The Visual6502 project F.A.Q.
  10. ^ "Inside the RCA CDP1802".
  11. ^ "Oral History of Federico Faggin".
  12. ^ Frank Völkel. "New CPUs, Old Boards: Athlon XP 2800+ Starting From KT333". 2002. [8]
  13. ^ [9]
  14. ^ "Copper Interconnect Architecture"
  15. ^ "IC Knowledge Cost and Price Model Supported Process List"

Further reading[edit]

  • Silicon VLSI Technology: Fundamentals, Practice, and Modeling. Prentice Hall 2000, ISBN 0-13-085037-3 Chapter 11 "Back End Technology" pages 681-786
  • "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. [10] pages 177-179 (Chapter 7.2 CMOS Process Integration); pages 199-208 (7.2.2 Backend-of-the-line Integration)

See also[edit]