Brent–Kung adder

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In electronics, an adder is a combinatorial or sequential logic element which computes the (n+1)-bit sum of two n-bit numbers. The Brent–Kung adder proposed in 1982 [1] is one of the most advanced designs, having a gate level depth of O(log_2(n)).

The Brent–Kung adder is a parallel prefix form carry look-ahead adder. It takes less area to implement than the Kogge-Stone adder and has less wiring congestion, but higher delay.

Introduction[edit]

Brent-kung adder is a parallel adder made in regular fashion with an aim of minimizing the chip area and ease of manufacturing. The addition of n-bit number can be performed in time O(log n) with a chip size of area O(nlog n), thus making it a first adder made with a constraint on area and maximizing the performance. Its symmetry and regular fashion built up reduces its cost of production effectively.

Basic Model Outline[edit]

In general, most of the adders use carry in and the corresponding bits of two numbers (A and B) to get the corresponding sum bit and carry out.But this adder is quite different from them.Brent-kung adder is a parallel prefix form i.e. it uses generate constant and propagate constant to do the computation and find out the sum result and carry out.

Let us consider
A = anan-1....a0 and
B = bnbn-1....b0
both be a n-bit binary numbers.Let there Sum be
S = sn+1an....a0

We know from the concept of adder
ci = ai.bi + bi.ci-1 + ci-1.ai and si = ai XOR bi XOR ci-1

References[edit]

  1. ^ Brent, R. P. & Kung, H. T. "A Regular Layout for Parallel Adders". IEEE Transactions on Computers, 1982, C-31, 260-264

External links[edit]