|Produced||From late 2011 to present|
|Min. feature size||32 nm|
Bulldozer is designed from scratch, not a development of earlier processors. The core is specifically aimed at 10 to 125 watt TDP computing products. AMD claims dramatic performance-per-watt efficiency improvements in high-performance computing (HPC) applications with Bulldozer cores.
The Bulldozer cores support most of the instruction sets implemented by Intel processors available at its introduction (including SSE4.1, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD; ABM (Advanced Bit Manipulation), XOP, FMA4 and CVT16.
- 1 Overview
- 2 Architecture
- 3 Processors
- 4 Performance
- 5 Future revisions
- 6 See also
- 7 References
- 8 External links
According to AMD, Bulldozer-based CPUs are based on GlobalFoundries' 32 nm Silicon on insulator (SOI) process technology and reuses the approach of DEC for multitasking computer performance with the arguments that it, according to press notes, "balances dedicated and shared computer resources to provide a highly compact, high units count design that is easily replicated on a chip for performance scaling." In other words, by eliminating some of the "redundant" elements that naturally creep into multicore designs, AMD has hoped to take better advantage of its hardware capabilities, while using less power.
Bulldozer-based implementations built on 32nm SOI with HKMG arrived in October 2011 for both servers and desktops. The server segment included the dual chip (16-core) Opteron processor codenamed Interlagos (for Socket G34) and single chip (4, 6 or 8 cores) Valencia (for Socket C32), while the Zambezi (4, 6 and 8 cores) targeted desktops on Socket AM3+.
Bulldozer is the first major redesign of AMD’s processor architecture since 2003, when the firm launched its K8 processors, and also features two 128-bit FMA-capable FPUs which can be combined into one 256-bit FPU. This design is accompanied by two integer clusters, each with 4 pipelines (the fetch/decode stage is shared). Bulldozer also introduced shared L2 cache in the new architecture. AMD's marketing service calls this design a "Module". A 16-core processor design would feature eight of these "modules", but the operating system will recognize each "module" as two logical cores.
The modular architecture consists of multithreaded shared L2 cache and FlexFPU, which uses simultaneous multithreading. Each physical integer core, two per module, is single threaded, in contrast with Intel's Hyperthreading, where two virtual simultaneous threads share the resources of a single physical core.
- AMD has re-introduced the "Clustered Integer Core" micro-architecture, an architecture developed by DEC in 1996 with the RISC microprocessor Alpha 21264. This technology is informally called CMT (Clustered Multi-Thread) and formally called "module" by the AMD. In terms of hardware complexity and functionality, this "module" is equal to a dual-core processor in its integer power (each thread having a fully independent integer core). While it is similar to a single core processor that has the SMT ability, which can create a dual threads processor but with the power of one (each thread shares the resources of the module with the other thread) in terms of floating point performance.
- A "module" consists in a coupling of two "conventional" x86 out-of-order processing cores. The processing core shares the early pipeline stages (e.g. L1i, fetch, decode), the FPUs, and the L2 cache with the rest of the "module".
- Each "module" has the following independent hardware resources:
- 2 MB of L2 cache per "Module" (shared between the two integer clusters in the Core)
- 16 KB 4-way of L1d (way-predicted) per cluster and 2-way 64 KB of L1i per core, one way for each of the two cluster
- Two dedicated integer clusters
- each one consists of two ALU and two AGU which are capable for total of four independent arithmetic and memory operations per clock and per cluster
- duplicating integer schedulers and execution pipelines offers dedicated hardware to each of two threads which increase performance in some multi-threaded integer case
- the second integer cluster increases the Bulldozer core die by around 12%, which at chip level adds about 5% of total die space
- Two symmetrical 128-bit FMAC (fused multiply–add capability) floating-point pipelines per module that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches AVX instruction and two symmetrical x87/MMX/SSE capable FPPs for backward compatibility with SSE2 non-optimized software
- All "modules" present share the L3 cache as well as an Advanced Dual-Channel Memory Sub-System (IMC - Integrated Memory Controller).
- A "module" has 213 millions transistors in an area of 30.9 mm² (including the 2 MB shared L2 cache) on an Orochi die
Instruction set extensions
- Support for Intel's Advanced Vector Extensions (AVX) instruction set, which supports 256-Bit floating point operations, and SSE4.1, SSE4.2, AES, CLMUL, as well as future 128-bit instruction sets proposed by AMD (XOP, FMA4 and CVT16), which have the same functionality as the SSE5 instruction set formerly proposed by AMD, but with compatibility to the AVX coding scheme.
Process technology and clock frequency
- 11-metal layer 32 nm SOI process with implemented first generation GlobalFoundries's High-K Metal Gate (HKMG)
- Turbo Core 2 performance boost to increase clock frequency up to 500 MHz with all threads active (for most workloads) and up to 1 GHz with the half of the thread active, within the TDP limit.
- The chip operates at 0.775 to 1.425 V, achieving clock frequencies of 3.6 GHz or more
- Min-Max TDP: 25 – 140 watts
Cache and memory interface
- Up to 8 MB of L3 shared among all Cores on the same silicon die (8 MB for 4 Cores in Desktop segment and 16 MB for 8 Cores in the Server segment), divided into four subcaches of 2 MB each, capable of operating at 2.2 GHz at 1.1125 V
- Native DDR3 memory support up to DDR3-1866
- Dual Channel DDR3 integrated memory controller for Desktop and Server/Workstation Opteron 42xx "Valencia"; Quad Channel DDR3 Integrated Memory Controller  for Server/Workstation Opteron 62xx "Interlagos"
- AMD claims support for two DIMMs of DDR3-1600 per channel. Two DIMMs of DDR3-1866 on a single channel will be down-clocked to 1600.
I/O and socket interface
- HyperTransport Technology rev. 3.1 (3.20 GHz, 6.4 GT/s, 25.6 GB/s & 16-bit wide link) [first implemented into HY-D1 revision "Magny-Cours" on the socket G34 Opteron platform in March 2010 and "Lisbon" on the socket C32 Opteron platform in June 2010]
- Socket AM3+ (AM3r2)
- For the server segment, the existing socket G34 (LGA1974) and socket C32 (LGA1207) will be used.
The first revenue shipments of Bulldozer-based Opteron processors was announced on September 7, 2011. The FX-4100, FX-6100, FX-8120 and FX-8150 were released in October 2011; with remaining FX series AMD processors released at the end of the first quarter of 2012.
|Frequency||Max. Turbo||L2 Cache||L3 Cache||TDP||Memory||Turbo Core||Socket|
|Full Load||Half Load|
|FX-8150||4 (8)||3.6 GHz||3.9 GHz||4.2 GHz||4 x 2 MB||8 MB||125 W||DDR3
|FX-8120||3.1 GHz||3.4 GHz||4.0 GHz|
|FX-8100||2.8 GHz||3.1 GHz||3.7 GHz||95 W|
|FX-6200||3 (6)||3.8 GHz||4.0 GHz||4.1 GHz||3 x 2 MB||125 W|
|FX-6120||3.5 GHz||3.9 GHz||4.1 GHz||95 W|
|FX-6100||3.3 GHz||3.6 GHz||3.9 GHz|
|FX-4170||2 (4)||4.2 GHz||4.3 GHz||4.3 GHz||2 x 2 MB||125 W|
|FX-4130||3.8 GHz||3.9 GHz||4.0 GHz||4 MB|
|FX-4100||3.6 GHz||3.7 GHz||3.8 GHz||8 MB||95 W|
AMD plans two series of Bulldozer-based processors for servers: Opteron 4200 series (code named Valencia, with up to eight cores) and Opteron 6200 series (code named Interlagos, with up to 16 cores).
Performance on Linux
On 24 October 2011, the first generation tests done by Phoronix confirmed that the performance of Bulldozer CPU is somewhat less than expected. In many tests the CPU has performed on same level as older generation Phenom 1060T.
Performance on Windows
The first Bulldozer CPUs were met with a mixed response. It was discovered that the FX-8150 performed poorly in benchmarks that were not highly threaded, falling behind the second-generation Intel Core i* series processors and being matched or even outperformed by AMD's own Phenom II X6 at lower clock speeds. In highly threaded benchmarks, the FX-8150 performed on par with the Phenom II X6, and the Intel Core i7 2600K, depending on the benchmark. Given the overall more consistent performance of the Intel Core i5 2500K at a lower price, these results left many reviewers underwhelmed. The processor was found to be extremely power-hungry under load, especially when overclocked, compared to Intel's Sandy Bridge.
The Tom's Hardware website commented that the lower-than-expected performance in multi-threaded workloads may be because of the way Windows 7 currently schedules threads to the cores. They point out that "if Windows were able to utilize an FX-8150's four modules first, and then backfill each module's second core, it'd maximize performance with up to four threads running concurrently." This is similar to what happens on Intel CPUs with HyperThreading – Windows 7 "schedules to physical cores before utilizing logical (HyperThreaded) cores."
On 13 October 2011, AMD stated on its blog that "there are some in our community who feel the product performance did not meet their expectations", but showed benchmarks on actual applications where it outperformed the Sandy Bridge i7 2600k and AMD X6 1100T.
On 6 March 2012, AMD posted a knowledge base article stating that there was a compatibility problem with FX processors, and certain games on the widely used digital game distribution platform, Steam. AMD stated that they had provided a BIOS update to several motherboard manufacturers (namely: Asus, Gigabyte Technology, MSI, and ASRock) that would fix the problem.
On 31 August 2011, AMD and a group of well-known overclockers including Brian McLachlan, Sami Mäkinen, Aaron Schradin, and Simon Solotko managed to set a new world record for CPU frequency using the unreleased and overclocked FX-8150 Bulldozer processor. Before that day, the record sat at 8.309 GHz, but the Bulldozer combined with liquid helium cooling reached a new high of 8.429 GHz. The record has since been over taken at 8.58 GHz by Andre Yang using LN2. 
2nd Generation (Piledriver)
Piledriver is the AMD given codename to an improved microarchitecture based on Bulldozer. AMD Piledriver cores are found in Socket FM2 Trinity and Richland based series of APUs and CPUs and the Socket AM3+ Vishera based FX-series of CPUs.
3rd Generation (Steamroller)
Steamroller is the AMD codename for their microarchitecture based on an improved version of Piledriver. Steamroller cores will be found in the upcoming Socket FM2+ Kaveri based series of APUs and CPUs.
4th Generation (Excavator)
On 12 October 2011, AMD revealed Excavator to be the codename for the 4th generation Bulldozer core. Excavator will initially be implemented in the 4th Generation A-series Fusion APU line in 2015. Reports indicate this APU will be codenamed Carrizo.
- Piledriver (microarchitecture)
- Steamroller (microarchitecture)
- List of AMD CPU microarchitectures
- List of AMD FX microprocessors
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