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The F16C (previously/informally known as CVT16) instruction set is x86 instruction set architecture extension which provide support for converting between half-precision and standard IEEE single-precision floating-point formats.
CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007, which is supplemented by the XOP and FMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged.
The instructions are abbreviations for "vector convert packed half to packed single" and vice versa:
VCVTPH2PS xmmreg,xmmrm64– convert four half-precision floating point values in memory or the bottom half of an XMM register to four single-precision floating-point values in an XMM register.
VCVTPH2PS ymmreg,xmmrm128– convert eight half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to eight single-precision floating-point values in a YMM register.
VCVTPS2PH xmmrm64,xmmreg,imm8– convert four single-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register.
VCVTPS2PH xmmrm128,ymmreg,imm8– convert eight single-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register.
The 8-bit immediate argument to
VCVTPS2PH selects the rounding mode. Values 0–4 select nearest, down, up, truncate, and the mode set in MXCSR.RC.
Support for these instructions is indicated by bit 29 of ECX after CPUID with EAX=1.
- AMD64 Architecture Programmer's Manual Volume 1 
- AMD64 Architecture Programmer's Manual Volume 2 
- AMD64 Architecture Programmer's Manual Volume 3 
- AMD64 Architecture Programmer's Manual Volume 4 
- AMD64 Architecture Programmer's Manual Volume 5 
- IA32 Architectures Software Developer Manual