Category:Electronic design automation

C

• ► Electronic design automation companies‎ (63 P)
• ► Electronic design automation conferences‎ (7 P)

E

• ► EDA file formats‎ (16 P)
• ► Electronic circuit verification‎ (20 P)
• ► Electronic design automation software‎ (3 C, 47 P)

H

• ► Hardware description languages‎ (2 C, 43 P)
• ► Hardware verification languages‎ (10 P)

I

• ► IEEE DASC standards‎ (9 P)

N

• ► Network On Chip‎ (3 P)

O

• ► Electronics optimization‎ (14 P)

O cont.

• ► Electronic design automation organizations‎ (4 P)

P

• ► Electronic design automation people‎ (13 P)

S

• ► SMT solvers‎ (2 P)

T

• ► Timing in electronic circuits‎ (1 C, 10 P)

• Electronic design automation

A

• Algorithmic State Machine
• And-inverter graph
• Antenna effect
• Asynchronous system

B

• Black's equation
• Boolean satisfiability problem

C

• Cell (EDA)
• Channel router
• Circuit extraction

D

• Design closure
• Design flow (EDA)
• Design for manufacturability (IC)
• Design for testing
• Digital electronics
• Dolphin Integration

E

• EDA database
• Electromagnetic field solver
• Electromigration
• Electronic circuit simulation
• Electronic system-level design and verification
• Elmore delay
• Engineering Change Order

F

• Fault coverage
• Feedback controlled electromigration
• Fiduccia-Mattheyses algorithm
• Floorplan (microelectronics)

G

• Generic array logic
• Graphical system design

H

• Hardware obfuscation

H cont.

• High-level synthesis
• High-level verification

I

• IC layout editor
• IEC 61131-3
• Input/output Buffer Information Specification

L

• Ladder logic
• Lee algorithm
• Logic optimization
• Logic simulation
• Logic synthesis

M

• Mask data preparation
• Maze runner
• Multi-channel length
• Multi-project wafer service

N

• Netlist
• Network On Chip
• Noise margin

P

• PBIST
• Physical design (electronics)
• Place and route
• Placement (EDA)
• Platform-based design
• Potential applications of carbon nanotubes
• Power gating
• Power network design (IC)
• Power optimization (EDA)
• Programmable Array Logic
• Programmable logic array
• Programmable system device

R

• Register-transfer level

R cont.

• Rent's rule
• Resolution enhancement technologies
• Routing (electronic design automation)

S

• Satisfiability Modulo Theories
• SCALD
• Schematic
• Schematic capture
• Schematic editor
• Semiconductor device modeling
• Semiconductor intellectual property core
• Semiconductor process simulation
• Signal integrity
• Signoff (electronic design automation)
• Silicon compiler
• Simulation software
• Standard cell
• State logic
• Stuck-at fault
• Substrate coupling
• Symbolic simulation
• Systems design

T

• Technology CAD
• Test compression
• Touchstone file
• Transaction-level modeling

U

• Ultra-large-scale systems
• Universal Verification Methodology
• Upverter