Centaur Technologies Inc. was founded in April 1995 by Glenn Henry, Terry Parks, Darius Gaskins, and Al Sato. The funding came from Integrated Device Technology, Inc (IDT). The business goal was to develop compatible x86 processors that were much less expensive than Intel processors and consumed much less power.
There were two fundamental elements of the plan. First, a unique design, developed from scratch, of an x86 processor core optimized differently than Intel's cores. Second, a unique management approach designed to achieve high productivity.
While founded by IDT, three different Centaur designs were shipped under the marketing name of WinChip. In September 1999, Centaur was purchased from IDT by VIA Technologies, a Taiwanese company. Since then, five designs have shipped with marketing name of VIA C3, quite a number of designs as the VIA C7 processor, and their latest 64-bit CPU, the VIA Nano.
While slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock for clock basis, Centaur's chips are much smaller, cheaper to manufacture and consume less power. This makes them highly attractive in the embedded marketplace, and increasingly in the mobile sector as well.
A performance gap exists between Centaur and competing x86 chips. Centaur design philosophy was always centered around "sufficient" performance for tasks that its target market demands. Some of the design trade offs made by the design team run contrary to accepted wisdom.
In a trend-setting move, processors were designed with hardware encryption acceleration starting with the VIA C7. Following its release many Intel and AMD processors incorporate this feature.
- VIA Nano Isaiah (CN) is a combination of a number of firsts from Centaur, their first superscalar out-of-order CPU, their first 64-bit CPU and their first processor designed from scratch.
- The development of the VIA Nano focused on radically improving the performance side of the performance-per-watt equation while still maintaining a similar TDP to the VIA C7.
- VIA C7 Esther (C5J) as an evolutionary step after VIA C3 Nehemiah+ (C5P), in which Centaur followed their traditional approach of balancing performance against a constrained transistor / power budget.
- The cornerstone of the VIA C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache and branch prediction mechanisms.
- In the case of VIA C7, the design team have focused on further streamlining the "front-end" of the chip, i.e. cache size, associativity and throughput as well as the prefetch system. At the same time no significant changes to the execution core ("back-end") of the chip seem to have been made.
- The VIA C7 successfully further closes the gap in performance with AMD / Intel chips, since clock speed is not thermally constrained.
- Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where features were not sacrificed to save die space. In fact, generous primary caches (128KB) have always been a distinctive hallmark of Centaur designs.
- Generally, clock frequency is favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios.
- The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer clock-cycles than on other x86 processors.
- Rarely used x86 instructions are implemented in microcode and emulated as combinations of other x86 instructions. This saves die space and contributes to low power consumption. The impact upon the majority of real world application scenarios is minimal.
- These design principles are derivative from the original RISC advocates, who claim that a smaller set of instructions, better optimized, can deliver faster overall CPU performance. The C3 design cannot be considered a pure RISC design because it accepts the x86 instruction set which is a CISC design.
Comparative die size
130 nm (mm²)
90 nm (mm²)
65 nm (mm²)
|VIA Nano 1000/2000||1024||N/A||N/A||63.3|
|VIA C3 / VIA C7||64/128||52||30||N/A|
NOTE: Even the 180 nm Duron Morgan core (106 mm²) with a mere 64 K secondary cache, when shrunk down to a 130 nm process, would have still had a die size of 76 mm². The VIA x86 core is clearly the smallest and cheapest to produce. As can be seen in this table, almost four C7 cores could be manufactured for the same cost as a single core P4 Prescott on 90 nm process; this because it costs about the same amount to manufacture a given surface area for most types of chip - with just over a quarter of the surface area of a Prescott P4, the VIA C7 costs around a quarter as much to manufacture.
- Besedin, Dmitri. "Detailed Platform Analysis in RightMark Memory Analyzer. Part 12: VIA C7/C7-M Processors". Digit-Life.com. Retrieved 2007-03-12.