Common Power Format

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The Si2 Common Power Format, or CPF is a file format for specifying power-saving techniques early in the design process. In the design of integrated circuits, saving power is a primary goal, and designers are forced to use sophisticated techniques such as clock gating, multi-voltage logic, and turning off the power entirely to inactive blocks. These techniques require a consistent implementation in the design steps of logic design, implementation, and verification. For example, if multiple different power supplies are used, then logic synthesis must insert level shifters, place and route must deal with them correctly, and other tools such as static timing analysis and formal verification must understand these components. As power became an increasingly pressing concern, each tool independently added the features needed. Although this made it possible to build low power flows, it was difficult and error prone since the same information needed to be specified several times, in several formats, to many different tools. CPF was created as a common format that many tools can use to specify power-specific data, so that power intent only need be entered once and can be used consistently by all tools. The aim of CPF is to support an automated, power-aware design infrastructure.

Associated with CPF is the Power Forward Initiative (PFI), a group of companies that collaborate to drive low-power design methodology and have contributed to the development of the CPF v1.0 specification. PFI membership spans EDA, IP, library, foundry fabs, ASIC, IDM, and equipment companies. In March 2007, CPF v1.0 was contributed to the Silicon Integration Initiative (Si2) where it was ratified by Si2’s Low Power Coalition (LPC) as a Si2 standard. The LPC controls the ongoing evolution of the CPF v1.0 standard.

Contents[edit]

Constructs expressing power domains and their power supplies:

  • Logical design: hierarchical modules can be specified as belonging to specific power supply domains
  • Physical design: explicit power/ground nets and connectivity can be specified per cell or block.
  • Analysis: different timing library data for cases where the same cell is used in different power domains

Power control logic

  • Specification of level shifter logic - special cells needed when signals traverse between blocks of different supply voltage.
  • Specification of isolation logic - what special logic is needed for signals that traverse between blocks that can be powered up and down independently.
  • Specification of state-retention logic - when blocks are switched off entirely, how is the state retained?
  • Specification of switch logic and control signals - how are blocks switched on and off?

Definition and verification of power modes (standby, sleep, etc.)

  • Mode definitions
  • Mode transition expressions

History and controversy[edit]

Cadence Design Systems designed the early versions of CPF,[1] then contributed it to Si2. This was followed shortly by an alternative effort, the Unified Power Format or UPF, proposed as an IEEE standard as opposed to an Si2 standard. UPF has been driven mainly by Synopsys, Mentor Graphics and Magma. The technical differences between the two formats are relatively minor, but the political considerations are harder to overcome.[2][3] Not surprisingly, the Cadence Low-Power Solution supports Si2’s CPF, whereas the Synopsys, and Mentor Graphics offerings all support UPF. Magma supports both CPF and UPF.

An attempt at convergence is taking place in the Low Power Coalition at Si2.[4]

References[edit]

  1. ^ Chi-Ping Hsu, Pushing Power Forward with a Common Power Format - The Process of Getting it Right, EETimes, 5 Nov 2006
  2. ^ Goering, Richard, IC power standards convergence falters, EETimes, 21 March 2007
  3. ^ Goering, Richard, IEEE's patent policy fails to quell EDA standards row, EEtimes, 30 April 2007.
  4. ^ Silicon Integration Initiative, CPF 1.2 Roadmap, 17 September 2008.

External links[edit]