Comparison of instruction set architectures

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Computer architectures are often described as n-bit architectures. Today n is often 8, 16, 32, or 64, but other sizes have been used. This is actually a strong simplification. A computer architecture often has a few more or less "natural" datasizes in the instruction set, but the hardware implementation of these may be very different. Many architectures have instructions operating on half and/or twice the size of respective processors major internal datapaths. Examples of this are the 8080, Z80, MC68000 as well as many others. On this type of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a 32-bit architecture with a 16-bit implementation. The external databus width is often not useful to determine the width of the architecture; the NS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. The NS32764 had a 64-bit bus, but used 32-bit registers.

The width of addresses may or may not be different from the width of data. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors.


The number of operands is one of the factors that may give an indication about the performance of the instruction set. A three-operand architecture will allow

A := B + C

to be computed in one instruction.

A two-operand architecture will allow

A := A + B

to be computed in one instruction, so two instructions will need to be executed to simulate a single three-operand instruction

A := B
A := A + C


An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little endian processors order bytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big endian architectures instead order them with the most significant byte at the lowest-numbered address. The x86 and the ARM architectures as well as several 8-bit architectures are little endian. Most RISC architectures (SPARC, Power, PowerPC, MIPS) were originally big endian, but many (including ARM) are now configurable.

Instruction sets[edit]

Usually numer of "registers" are a power of two, eg. 8, 16, 32. Often however, one of those is hardwired to zero, and then not a really a register and is not counted below. In addition, sometimes there are registers, that are counted below, that are not general purpose. Then again, some special purpose registers (and non-architected registers for register renaming) are not counted.

The table below compares basic information about instruction sets to be implemented in the CPU architectures:

Instruction set Bits Version Introduced Max # operands Type Design Registers Instruction encoding Branch evaluation Endianness Extensions Open Royalty free
Alpha 64 1992 3 Register Register RISC 32 Fixed (32-bit) Condition register Bi MVI, BWX, FIX, CIX No Unknown
ARM 32 ARMv7 and earlier 1983 3 Register Register RISC 16 (including PC and SP) Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit) Condition code Bi NEON, Jazelle, VFP, TrustZone, LPAE Unknown No
ARMv8-A 64/32 ARMv8-A[1] 2011[2] 3 Register Register RISC 31 Fixed (32-bit). In ARMv7 compatibility mode: Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit), A64 Condition code Bi NEON, Jazelle, VFP, TrustZone Unknown No
AVR32 32 Rev 2 2006 2-3 RISC 15 Variable[3] Big Java Virtual Machine Unknown Unknown
Blackfin 32 2000 RISC[4] 8 Little[5] Unknown Unknown
DLX 32 1990 3 RISC 32 Fixed (32-bit) Big Unknown Unknown
eSi-RISC 16/32 2009 3 Register Register RISC 8-72 Variable (16 or 32-bit) Compare and branch and condition register Bi User-defined instructions No No
Itanium (IA-64) 64 2001 Register Register EPIC 128 Condition register Bi (selectable) Intel Virtualization Technology No No
M32R 32 1997 RISC 16 Fixed (16- or 32-bit) Bi Unknown Unknown
Motorola 68k 32 1979 2 Register Memory CISC 8 data and 8 address Variable Condition register Big Unknown Unknown
Mico32 32 2006 3 Register Register RISC 32[6] Fixed (32-bit) Compare and branch Big User-defined instructions Yes[7] Yes
MIPS 64 (32→64) 5 1981 1-3 Register Register RISC 4-31 Fixed (32-bit) Condition register Bi MDMX, MIPS-3D Unknown No
MMIX 64 1999 3 Register Register RISC 256 Fixed (32-bit) Big Yes Yes
6502 8 1975 1 Register Memory CISC 1 Variable (8 to 32 bits) Condition register Little
65k 64 (8→64)[8] 2006? 1 Memory Memory[citation needed] CISC 1 Variable (8 bits to 256 bytes) Compare and branch[citation needed] Little
NS320xx 32 1982 5 Memory Memory CISC 8 Variable Huffman coded, up to 23 bytes long Condition Code Little BitBlt instructions Unknown Unknown
PA-RISC (HP/PA) 64 (32→64) 2.0 1986 3 Register Register RISC 32 Fixed (32-bit) Compare and branch Big → Bi Multimedia Acceleration eXtensions (MAX), MAX-2 No Unknown
PowerPC 32/64 (32→64) 2.07[9] 1991 3 Register Register RISC 32 Fixed (32-bit), Variable Condition code Big/Bi AltiVec, APU, VSX, Cell Yes[10] No
S+core 16/32 2005 RISC Little Unknown Unknown
SPARC 64 (32→64) V9 1985 3 Register Register RISC 31 (of at least 55) Fixed (32-bit) Condition code Big → Bi VIS 1.0, 2.0, 3.0 Yes Yes[11]
SuperH (SH) 32 1990s 2 Register Register / Register Memory RISC 16 Fixed (16- or 32-bit), Variable Condition Code (Single Bit) Bi Unknown Unknown
System/360 / System/370 / z/Architecture 64 (32→64) 3 1964 Register Memory / Memory Memory CISC 16 Variable Condition code Big Unknown Unknown
VAX 32 1977 6 Memory Memory CISC 16 Variable Compare and branch Little VAX Vector Architecture Unknown Unknown
x86 32 (16→32) 1978 2 Register Memory CISC 8 (including SP and BP) Variable Condition code Little MMX, 3DNow!, SSE, PAE No No
x86-64 64 (32→64) 2003 2 (integer)
3 (AVX)
Register Memory CISC 16 (including SP and BP) Variable Condition code Little MMX, 3DNow!, PAE, AVX, AES, FMA No No
Z80 8 1976 2 Register Memory CISC 8 Variable (8 to 32 bits) Condition register Little
Xilinx 4→48→56 2005 1 Condition Code FPGA 1 Variable (up to 768 bytes) Condition register Little
Crusoe 32 2000 1 Register Register[12] VLIW[12][13] 64[12][13] Variable (64 or 128 bits)[13] Condition code[12] Little
Architecture Bits Version Introduced Max # operands Type Design Registers Instruction encoding Branch evaluation Endianness Extensions Open Royalty free

See also[edit]


  1. ^ ARMv8 Technology Preview
  2. ^ "ARM goes 64-bit with new ARMv8 chip architecture". Retrieved 26 May 2012. 
  3. ^ "AVR32 Architecture Document". Atmel. Retrieved 2008-06-15. 
  4. ^ "Blackfin Processor Architecture Overview". Analog Devices. Retrieved 2009-05-10. 
  5. ^ "Blackfin memory architecture". Analog Devices. Retrieved 2009-12-18. 
  6. ^ "LatticeMico32 Architecture". Lattice Semiconductor. Retrieved 2009-12-18. 
  7. ^ "Open Source Licensing". Lattice Semiconductor. Retrieved 2009-12-18. 
  8. ^ "The 65k Project". Advanced 6502. Retrieved 20 December 2013. 
  9. ^ "Power ISA 2.07". IBM. Retrieved 2013-08-12. 
  10. ^ New to Cell/B.E., multicore, and Power Architecture technology
  11. ^ SPARC Architecture License
  12. ^ a b c d "Crusoe Exposed: Transmeta TM5xxx Architecture 2". Real World Technologies. 
  13. ^ a b c Alexander Klaiber (January 2000). "The Technology Behind Crusoe Processors". Transmeta Corporation. Retrieved December 6, 2013.