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In digital circuits, the contamination delay, tcd, is the minimum amount of time when an input changes until any output start to change its value. This change in value does not imply that the value has reached a stable condition. The contamination delay only specifies that the output rises (or falls) to 50% of the voltage level for a logic high. The Circuit is guaranteed not to show any output change in response to an input change before tcd time units (calculated for the whole circuit) have passed. The determination of the contamination delay of a combined circuit requires identifying the shortest path of contamination delays from input to output and by adding each tcd time along this path.
For a sequential circuit such as two D-flip flops connected in series, the contamination delay of the first flip-flop must be factored in to avoid violating the hold-time constraint of the second flip-flop receiving the output from the first flip flop. Here, the contamination delay is the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q). If there is insufficient delay from the output of one flip-flop to the input of the next, the input may change before the hold time has passed. Because the second flip-flop is still unstable, its data would then be "contaminated." Every path from an input to an output can be characterized with a particular contamination delay.
Well-balanced circuits will have similar speeds for all paths through a combinational stage, so the minimum propagation time is close to the maximum. This corresponding maximum time is the propagation delay. The condition of data being contaminated is called a race.
References: 1. http://www.nileshgoel.com/wp-content/uploads/2010/02/timing-note.pdf 2. http://6004.csail.mit.edu/Spring04/handouts/L04-4up.pdf 3. David Money Harris & Sarah L. Harris, Digital Design and Computer Architecture, ISBN 9780123944245, Printbook, Release Date: 2012.
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