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Graphic of a running hare in black and white above text "coreboot" in lowercase sans-serif font.
Original author(s) Ronald G. Minnich, Eric Biederman, Li-Ta (Ollie) Lo, Stefan Reinauer, the coreboot community
Initial release 1999
Stable release Rolling release
Development status active
Written in Mostly C, and about 1% in assembly
Platform x86 x86-64, ARMv7[1]
Type Firmware
License GPLv2

coreboot (formerly known as LinuxBIOS[2]) is a free software project, aimed at replacing the proprietary BIOS firmware found in most computers with a lightweight system designed to perform only the minimum number of tasks necessary to load and run a modern 32-bit or 64-bit operating system.


The coreboot project began in the winter of 1999 in the Advanced Computing Laboratory at Los Alamos National Laboratory (LANL),[3] with the goal of creating a BIOS that would start fast and handle errors intelligently.[4] It is licensed under the terms of the GNU General Public License (GPL). Main contributors include LANL, SiS, AMD, Coresystems and Linux Networx, Inc, as well as motherboard vendors MSI, Gigabyte and Tyan, which offer coreboot alongside their standard BIOS or provide specifications of the hardware interfaces for some of their motherboards. However, Tyan seems to have ceased support of coreboot.[citation needed] Google partly sponsors the coreboot project.[5] CME Group, a cluster of futures exchanges, began supporting the coreboot project in 2009.[6]

Coreboot has been accepted in seven consecutive years (2007–2014) for the Google Summer of Code.[7][8] Other than the first three models, all Chromebooks run Coreboot.[9][10] Code from Das U-Boot has been assimilated to enable support for processors based on the ARM instruction set.[11]

Supported platforms[edit]

Besides x86 and x86-64 architectures, coreboot support also exists for the AMD Geode solutions. Support started with the Geode GX processor developed by AMD for the OLPC, Artec Group then added Geode LX support for its model DBE61 ThinCan. Recently, that code was adopted by AMD and further polished for the OLPC after they upgraded to the Geode LX platform. That code is now being further developed by the coreboot community to support other AMD Geode solutions. Coreboot can be flashed onto an AMD Geode platform using Flashrom.

From that initial development on AMD Geode based platforms, coreboot support has been extended onto many AMD processors and chipsets. The processor list includes Family 0Fh and 10h (K8 core), and recently Family 14h (Bobcat core, Fusion APU). Coreboot support also extends to AMD chipsets: RS690, RS7xx, SB600, and SB8xx.

AMD Generic Encapsulated Software Architecture (AGESA)—​a bootstrap protocol by which system devices on AMD64 mainboards are initialized—​was open sourced in early 2011, aiming to provide required functionality for coreboot system initialization on AMD64 hardware.[12]


Coreboot typically loads a Linux kernel, but it can load any other stand-alone ELF executable, such as iPXE, gPXE or Etherboot that can boot a Linux kernel over a network, or SeaBIOS[13] that can load a Linux kernel, Microsoft Windows 2000 and later, and BSDs (previously, Windows 2000/XP and OpenBSD support was provided by ADLO[14][15]). Coreboot can also load a kernel from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Booting other kernels directly is also possible, such as a Plan 9 kernel. Instead of loading a kernel directly, coreboot can pass control to a dedicated boot loader, such as a coreboot-capable version of GNU GRUB 2.

Coreboot is written primarily in C, with a small amount of assembly code. Choosing C as the primary programming language enabled easier code audits, which result in improved security. The source code is released under the GNU GPL version 2 license.

Coreboot performs the absolute minimal amount of hardware initialization and then passes control to the operating system. As a result, there is no coreboot code running once the operating system has taken control; in particular, System Management Mode (SMM) is not activated.[16] A feature of coreboot is that the x86 version runs in 32-bit mode after executing only ten instructions[17] (almost all other x86 BIOSes run exclusively in 16-bit mode). This is similar to the modern UEFI firmware, which is used on newer PC hardware.

By itself, coreboot does not provide BIOS call services. The SeaBIOS payload can be used to provide BIOS calls and thus allow coreboot to load operating systems that require those services, such as Windows 2000/XP/Vista/7 and BSDs. However, most modern operating systems access hardware in another manner and only use BIOS calls during early initialization and as a fallback mechanism.

Coreboot stages[edit]

  1. Bootblock stage: prepare to obtain Flash access and look up the ROM stage to use
  2. ROM stage: memory and early chipset init (a bit like PEI in EFI)
  3. RAM stage: device enumeration and resource assignment, ACPI table creation, SMM handler (a bit like DXE stage in EFI)
  4. Payload.

Initializing DRAM[edit]

The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation on this subject is NDA restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's general purpose registers or Cache-as-RAM as temporary storage.

romcc, a C compiler that uses registers instead of RAM, eases the task. Using romcc, it is relatively easy to make SMBus accesses to the SPD ROMs of the DRAM DIMMs, that allows the RAM to be used.

With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM[18][19] mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard.

Developing and debugging coreboot[edit]

Hacking Coreboot at Denver 2008 summit.

Since coreboot must initialize the bare hardware, it must be ported to every chipset and motherboard that it supports. Before initializing RAM, coreboot initializes the serial port (addressing cache and registers only), so it can send out debug text to a connected terminal. It can also send byte codes to port 0x80 that are displayed on a two-hex-digit display of a connected POST card.

Another porting aid is the commercial "RD1 BIOS Savior" product from IOSS,[20] which is a combination of two boot memory devices that plugs into the boot memory socket and has a manual switch to select between the two devices. The computer can boot from one device, and then the switch can be toggled to allow the computer to reprogram or "flash" the second device. A more expensive alternative is an external EPROM/flash programmer.

There are also CPU emulators that either replace the CPU or connect via a JTAG port, with the Sage SmartProbe[21] being an example. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.


SeaBIOS payload running on a Lenovo ThinkPad X60

Coreboot can load a payload. Payloads can be written using the libpayload helper-library, but it is not required. Existing payloads include:


Libreboot logo
Libreboot was established as a distribution of coreboot without proprietary binary blobs.[24][25] Endorsed by the Free Software Foundation (FSF),[26] the project made possible the required modifications for completely libre variants of some ThinkPad and MacBook laptops.[27][28]
The open-source SageBIOS is a custom version of coreboot implemented in custom-built OPNsense appliances. These Deciso "Netboard A10"-based[29] appliances use the embedded G-Series[30][31] SOC by AMD.[32][33][34]

See also[edit]


  1. ^ "Coreboot ARM". coreboot. 2013-10-15. Retrieved 2014-02-01. 
  2. ^ "[LinuxBIOS] Welcome to coreboot". 2008-01-12. 
  3. ^ coreboot FAQ: Who is working on coreboot?
  4. ^ Anton Borisov: The Open Source BIOS is Ten. An interview with the coreboot developers. The H, 2009.
  5. ^ Google Sponsors the LinuxBIOS project
  6. ^ CME Group Dives Into Coreboot
  7. ^ "Coreboot GSoC". Retrieved 2014-02-01. 
  8. ^ "Previous GSoC Projects". Retrieved 2014-02-01. 
  9. ^ Larabel, Michael (2012-04-22). "Many FSF Priority Projects Still Not Progressing". Phoronix. Retrieved 2014-12-29. The success out of Coreboot recently is Google providing Sandy/Ivy Bridge support for Coreboot. Google's planning to begin shipping new Intel "Chromebooks" that will use Coreboot. Google likes Coreboot for the faster start-up time, among other benefits. 
  10. ^ "Chromebooks". coreboot. 2014-01-16. Retrieved 2014-02-17. 
  11. ^ "GSoC2011(Week 1): Analysis of U-boot ARM boot code | coreboot developer blogs". Retrieved 2014-04-12. 
  12. ^ "Technical details on AMD's coreboot source code release". AMD. 2011-02-28. Retrieved 2014-07-02. 
  13. ^ SeaBIOS (previously known as LegacyBIOS) is an open-source legacy BIOS implementation
  14. ^ coreboot Add-on Layer (ADLO)
  15. ^ SEBOS, Security Enhanced Bootloader for Operating Systems, Phase 2 , adding PC BIOS Services to coreboot via Bochs BIOS (Link noted to be defunct on 18 July 2008. See SEBOS Phase 2 at the Wayback Machine (archived June 19, 2007))
  16. ^ Carl-Daniel Hailfinger. "On Coreboot". FOSDEM2012. 
  17. ^ coreboot v3 early startup code
  18. ^ Yinghai Lu; Li-Ta Lo; Gregory R. Watson; Ronald G. Minnich (2009-01-15). "CAR: Using Cache as RAM in Linux BIOS" (PDF). Retrieved 2014-02-25. 
  19. ^ A Framework for Using Processor Cache as RAM (CAR)
  20. ^ IOSS
  21. ^ Sage Engineering
  22. ^ Google Pushes "Project PIANO" Into Coreboot
  23. ^ "Modify u-boot code to allow building coreboot payload. [chromiumos/third_party/u-boot-next : chromeos-v2011.03]". 2011-07-24. 
  24. ^ "Libreboot". Free Software Foundation. Retrieved 31 July 2014. 
  25. ^ "Libreboot". Libreboot. Retrieved 31 July 2014. 
  26. ^ The Free Software Foundation's Campaign for Free BIOS
  27. ^ Gay, Joshua (9 October 2012). "Respects Your Freedom hardware product certification". Free Software Foundation. Retrieved 25 February 2015. 
  28. ^ "Hardware compatibility list". Libreboot. Retrieved 25 February 2015. 
  29. ^ Brown, Eric. "Linux-friendly network SBC taps new AMD G-Series SoCs". Rick Lehrbaum. Retrieved 1 March 2015. 
  30. ^ Shvets, Gennadiy. "AMD G-Series GX-416RA specifications". CPU-World. Retrieved 1 March 2015. 
  31. ^ "As an innovator in embedded networking solutions, AMD is proud to collaborate with Deciso to offer a new open source firewall alternative," said Scott Aylor, corporate vice president and general manager, AMD Embedded Solutions. "The AMD Embedded G-Series SOC enables Deciso to deliver an ultra-low power design for the new OPNsense firewall appliance, without comprising performance and stability." "Deciso delivers new open source turnkey firewall alternative". PR Newswire. January 9, 2015. Retrieved 1 March 2015. 
  32. ^ "AMD Embedded G-Series System-on-Chip (SOC)". AMD. Retrieved 2013-11-10. 
  33. ^ "Netboard A10". Deciso B.V. Retrieved 1 March 2015. 
  34. ^ Schellevis, Jos. "Under the Hood: AMD G-Series SOC Delivers the Horsepower for Next Generation Firewalls". Advanced Micro Devices, Inc. Retrieved 1 March 2015. 

Further reading[edit]

External links[edit]