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The Cromemco 4FDC Floppy Disk Controller is designed to interface both 5.25"- and 8.0"-inch floppy disk drives to the S-100 computer bus used in Cromemco and other IEEE 696 computers. It also contains an RS232 serial I/O channel with software-selectable baud rates from 110 to 76,800. In addition, it has a 1K resident 2708 ROM containing Cromemco's RDOS, the resident disk operating system.
The 4FDC was designed to drive Persci 277 8-inch single-density floppy drives. These drives were interesting in two respects
- They used a fast voice coil actuator and not a stepper motor to position the drive read write head
- The data separator electronics were on the drive itself
Due to the second fact, an unmodified 4FDC can not be used with 8-inch drives that don't have single-density data separators on the drive electronics. Later Cromemco disk controllers such as the 16FDC and 64FDC contained both single and double density data separators and the 64FDC also supplied write pre-compensation.
An aftermarket add-on board, the FDCX4 Double Density Upgrade Board for the 4FDC, was designed and marketed by JVB Electronics. The FDCX4 was a daughter board assembly that replaced the WD1771 single density disk controller chip on the 4FDC with a FD1791 (early production) or Fujitsu MB8876A (later production) double-density controller chip. The FDCX4, in addition to using an analog phase-locked-loop data separator in all modes, also used write-precompensation. These features allowed the FDCX4 equipped 4FDC to reliably use the Persci 277 drives, as well as other drives, in double-density mode.
Four switches on the 4FDC interface card are used to set the operation of the card. Switch 1 is the RDOS DISABLE switch. When this switch is ON the 1K ROM containing RDOS cannot be accessed by the computer. When this switch is OFF the RDOS program resides in the computer memory space from address 0xC000 to 0xC3FF.
Switch 2 is the RDOS disable after boot switch. If this switch is ON the 1K ROM containing RDOS will automatically be disabled after CDOS is bootstrapped in from a disk thus clearing memory space from 0xC000 to 0xC3FF for system use. (In this mode the ROM is actually disabled by an output to port 40H which is done automatically by CDOS). If switch 2 is OFF, RDOS remains in memory space even after CDOS is loaded.
RDOS contains two programs; 1) the CDOS bootstrap program and 2) the console monitor program. Switch 3 is the boot enable switch. When this switch is ON the bootstrap program will execute (thus loading CDOS) without first entering the monitor program. If this switch is off, RDOS begins in the console monitor mode permitting the bootstrap operation or other operations to be performed under console control.
Switch 4 is the initialization inhibit switch. When this switch is ON, diskettes cannot be initialized under software control thus preventing a "runaway," program from unintentionally altering the diskette initialization. This switch must be OFF when initializing diskettes.
Western Digital FD1771-1 interfaces
All signals from the drives are TTL-buffered and have 150 ohm pullups. Maxi and mini signals are wired and at the pullup side of the buffers. Signals, which do not apply to the mini (i.e., READY and SEP CLOCK), are disabled and pulled high when the mini is selected. Signals to the drives from the 1771 are TTL-buffered with separate buffers for mini and maxi connectors. The STEP output is stretched by IC37 to about 16 microseconds before going to the drives. The HLD (head load) output does not go directly to the drives but rather enables the drive select lines through IC10 Pin 1. Thus, the actual drive select signal to the drive is the coincidence of a latched drive selection (done at port 34H) and HLD from the 1771. Head loading time is determined by counters IC36 and 27. Timeout is controlled by the count loaded into lC3's by IC53. Signals DRQ, HLD, and INTRQ (or EOJ) are available at input port 34H (rC9). Various control signals are assigned to output port 34H and are latched by rcs 24 and 41.
Board Priority Chain
The 4FDC includes a ripple priority circuit which will defeat the interrupt acknowledge cycle of Priority IN/ is held low. If the 4FDC is allowed to perform the interrupt acknowledge, it will pull down its Priority Out/ line to signal others in the chain not to respond. This chain is compatible with the Cromemco TU-ART.