Current mode logic (CML), or source-coupled logic (SCL), is a differential digital logic family intended to transmit data at speeds between 312.5 Mbit/s and 3.125 Gbit/s across standard printed circuit boards.
The transmission is point-to-point, unidirectional, and is usually terminated at the destination with 50 Ω resistors to Vcc on both differential lines. CML is frequently used in interfaces to fiber optic components.
This technology has widely been used in design of high-speed integrated systems, such as in telecommunication systems (serial data transceivers, frequency synthesizers, etc.). The fast operation of CML circuits is mainly due to their lower output voltage swing compared to the static CMOS circuits as well as the very fast current switching taking place at the input differential pair transistors. One of the primary requirements of a current-mode logic circuit is that the current bias transistor must remain in saturation region in order to maintain constant current.
Applications in ultra low power: Recently, CML topology has been used in ultra-low power applications. Studies show that while the leakage current in the conventional static CMOS circuits is becoming a major challenge in lowering the energy dissipation, good control on current consumption in the CML topology makes them a very good candidate at extreme low power conditions. Called subthreshold CML or subthreshold source coupled logic (STSCL), the consumption of each gate can be reduced down to few tens of pico-Amperes.
- Low-voltage differential signaling (LVDS) A differential standard used primarily for signals between modules.
- JESD204B - a JEDEC Standard for serial data interfacing, http://www.analog.com/static/imported-files/tech_articles/JESD204B-Survival-Guide.pdf
- display controller – IC that produces the signal
- Serial Interface for Data Converters, JEDEC standard JESD204, April 2006
- "Understanding DVI‐D, HDMI And DisplayPort Signals". Retrieved 2013-10-30.
- A. Tajalli, E. Vittoz, E. Brauer, and Y. Leblebici, "Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept," ESSCIRC 2007.
- System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 – 3.125 Gbit/s Parallel Interfaces. OIF, October 2002.
- TFI-5: TDM Fabric to Framer Interface Implementation Agreement. OIF, September 16, 2003
- Introduction to LVDS, PECL, and CML, Maxim, http://pdfserv.maxim-ic.com/en/an/AN291.pdf
- Interfacing between LVPECL, VML, cml and LVDS Levels, http://focus.ti.com/lit/an/slla120/slla120.pdf
- For more details on design automation and low power design of CML circuits, see: http://lsm.epfl.ch