Cycles per instruction
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In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is one aspect of a processor's performance: the number of clock cycles that happen when an instruction is being executed. It is the multiplicative inverse of instructions per cycle.
Cycles Per Instruction is defined by the following:
Where IIC is the number of instructions for a given instruction type, CCI is the clock-cycles for a given instruction type, IC is the total instruction count. The summation sums over all instruction types for a given benchmarking process.
Let us assume a classic RISC pipeline, with the following 5 stages:
- Instruction fetch cycle (IF)
- Instruction decode/Register fetch cycle (ID)
- Execution/Effective address cycle (EX)
- Memory access (MEM)
- Write-back cycle (WB)
Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without pipelining, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5. Therefore without pipelining the number of cycles it takes to execute an instruction is 5. This is the definition of CPI.
With pipe lining we can improve the CPI by exploiting instruction level parallelism. For example, what if an instruction is fetched every cycle? We could theoretically have 5 instructions in the 5 pipeline stages at once (one instruction per stage). In this case, a different instruction would complete stage 5 in every clock cycle, and therefore on average we have one clock cycle per instruction (CPI = 1).
With a single-issue processor, the best CPI attainable is 1. However with multiple-issue processors, we may achieve even better CPI values. For example a processor that issues two instructions per clock cycle (see Superscalar) can achieve a CPI of 0.5 when two instructions are completing every clock cycle.
For the multi-cycle MIPS, there are 5 types of instructions:
If a program has:
- 50% R-type instructions
- 15% load instructions
- 25% store instructions
- 8% branch instructions
- 2% jump instructions
then, the CPI is:
- CPI = (4 × 50 + 5 × 15 + 4 × 25 + 3 × 8 + 3 × 2) / 100 = 4.05.
|Instruction type||Instruction count||Clock cycle count|
Determine the effective CPI, MIPS rate, and execution time for this program.
- Total instruction count = 100000.
- CPI = (45000*1 + 32000*2 + 15000*2 + 8000*2)/100000 = 155000/100000 = 1.55.
- Effective processor performance = MIPS = clock frequency/(CPI*1000000) = (400*1000000)/(1.55*1000000) = 258 MIPS.
- Execution time (T) = CPI*Instruction count*clock time = CPI*Instruction count/frequency = 1.55*100000/(400*1000000) = 1.55/4000 = 0.387 ms.
- Instructions per cycle (IPC)
- Instructions per second (IPS)
- Cycle per second (Hz)
- Megahertz myth
- The benchmark article provides a useful introduction to computer performance measurement for those readers interested in the topic.
- Advanced Computer Architecture by Kai Hwang, Chapter 1, Exercise Problem 1.1
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