In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random-access memory, is a modern type of dynamic random-access memory (DRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors.
DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance.
The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. With two transfers per cycle of a quadrupled clock signal, a 64-bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed megahertz (MHz) in megabytes per second (MB/s). With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.
The DDR3 standard permits DRAM chip capacities of up to 8 gibibits, and up to 4 ranks of 64 bits each for a total maximum of 64GiB per DDR3 DIMM. Because of a hardware limitation, first addressed in Ivy Bridge-E in 2013, most Intel CPUs only support up to 4 gibibit modules for 8GiB DIMMs. All AMD CPUs correctly support the full spec for 16GiB DDR3 DIMMs.
Compared to DDR2 memory, DDR3 memory uses 30% less power. This reduction comes from the difference in supply voltages: 1.8 V or 2.5 V for DDR2, and 1.5 V or 1.35 V for DDR3. The 1.5 V supply voltage works well with the 90 nanometer fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors to reduce leakage of current.
According to JEDEC, 1.575 volts should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission-critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level.
Another benefit is its prefetch buffer, which is 8-burst-deep. In contrast, the prefetch buffer of DDR2 is 4-burst-deep, and the prefetch buffer of DDR is 2-burst-deep. This advantage is an enabling technology in DDR3's transfer speed.
DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a 400–1066 MHz I/O clock. This is twice DDR2's data transfer rates (400–1066 MT/s using a 200–533 MHz I/O clock) and four the rate of DDR1 (200–400 MT/s using a 100–200 MHz I/O clock). High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffers is required.
Because the hertz is a measure of cycles per second, and no signal cycles more often than every other transfer, describing the transfer rate in units of MHz is technically incorrect, although very common. It is also misleading because various memory timings are given in units of clock cycles, which are half the speed of data transfers.
DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007 based on Intel's P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMD's first socket AM3 Phenom II X4 processors, released in February 2009, were their first to support DDR3.
DDR3 DIMMs have 240 pins and are electrically incompatible with DDR2. A key notch—located differently in DDR2 and DDR3 DIMMs—prevents accidentally interchanging them. Not only are they keyed differently, but DDR2 has rounded notches on the side and the DDR3 modules have square notches on the side.  DDR3 SO-DIMMs have 204 pins.
For the Skylake microarchitecture, Intel has also designed a SO-DIMM package named UniDIMM, which can use either DDR3 or DDR4 chips. The CPU's integrated memory controller can then work with either. The purpose of UniDIMMs is to handle the transition from DDR3 to DDR4, where pricing and availability may make it desirable to switch RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the notch is placed differently to avoid accidentally using in an incompatible DDR4 SO-DIMM socket.
While the typical latencies for a JEDEC DDR2 device were 5-5-5-15, some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333.
DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3.
As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release. CAS latency of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7 at 667 MHz (DDR3-1333) is 10.5 ns.
(CAS / Frequency (MHz)) × 1000 = X ns
(7 / 667) × 1000 = 10.49475 ns
Power consumption of individual SDRAM chips (or, by extension, DIMMs) varies based on many factors, including speed, type of usage, voltage, etc. Dell's Power Advisor calculates that 4 GB ECC DDR1333 RDIMMs use about 4 W each. By contrast, a more modern mainstream desktop-oriented part 8 GB, DDR3/1600 DIMM, is rated at 2.58 W, despite being significantly faster.
Intel Corporation officially introduced the eXtreme Memory Profile (XMP) Specification on March 23, 2007 to enable enthusiast performance extensions to the traditional JEDEC SPD specifications for DDR3 SDRAM.
DDR3L and DDR3U
The DDR3L (DDR3 Low Voltage) standard is an addendum to the JESD79-3 DDR3 Memory Device Standard specifying low voltage devices. The DDR3L standard is 1.35 V and has the label ’’PC3L’’ for its modules. Examples include DDR3L‐800, DDR3L‐1066, DDR3L‐1333, and DDR3L‐1600.
The DDR3U standard is 1.25 V and has the label ’’PC3U’’ for its modules.
On July 26, 2010, JEDEC Solid State Technology Association announced the publication of JEDEC DDR3L.
DDR3 Serial Presence Detect
Release 4 of the DDR3 Serial Presence Detect (SPD) document (SPD4_01_02_11) adds support for Load Reduction DIMMs and also for 16b-SO-DIMMs and 32b-SO-DIMMs.
On September 1, 2011, JEDEC Solid State Technology Association announced the publication of Release 4 of the DDR3 Serial Presence Detect (SPD) document.
JEDEC standard modules
|I/O bus clock
|Peak transfer rate
tRCD - Clock cycles between row activate and reads/writes
tRP - Clock cycles between row precharge and activate
Fractional frequencies are normally rounded down, but rounding up to 667 is common because of the exact number being 666⅔ and rounding to the nearest whole number. Some manufacturers also round to a certain precision or round up instead. For example, PC3-10666 memory could be listed as PC3-10600 or PC3-10700.
Note: All items listed above are specified by JEDEC as JESD79-3D. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest reported speed reached was equivalent to DDR3-2544, as of May 2010.
DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
In addition to bandwidth and capacity variants, modules can:
- Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.
- Be "registered", which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a register, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC3-6400R is a registered PC3-6400 module, and PC3-6400R ECC is the same module with ECC.
- Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
- Be Load Reduced modules, which are designated by LR and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides large overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.
Both FBDIMM and LRDIMM memory types are designed primarily to control the amount of electrical current flowing to and from the memory chips at any given time. They are not compatible with registered/buffered memory, and motherboards that require them usually will not accept any other kind of memory.
- DDR3 SDRAM components
- Introduction of asynchronous RESET pin
- Support of system-level flight-time compensation
- On-DIMM mirror-friendly DRAM pinout
- Introduction of CWL (CAS write latency) per clock bin
- On-die I/O calibration engine
- READ and WRITE calibration
- DDR3 modules
- Fly-by command/address/control bus with on-DIMM termination
- High-precision calibration resistors
- Are not backwards compatible—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard
- Technological advantages compared to DDR2
- Higher bandwidth performance, up to 2133 MT/s standardized
- Slightly improved latencies, as measured in nanoseconds
- Higher performance at low power (longer battery life in laptops)
- Enhanced low-power features
Development and market penetration
In May 2005, Desi Rhoden, chairman of the JEDEC committee responsible for creating the DDR3 standard, stated that DDR3 had been under development for "about 3 years". DDR3 was launched in 2007, but sales were not expected to overtake DDR2 until the end of 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008. (The same timescale for market penetration had been stated by market intelligence company DRAMeXchange over a year earlier in April 2007, and by Desi Rhoden in 2005.) The primary driving force behind the increased usage of DDR3 has been new Core i7 processors from Intel and Phenom II processors from AMD, both of which have internal memory controllers: the former requires DDR3, the latter recommends it. IDC stated in January 2009 that DDR3 sales would account for 29% of the total DRAM units sold in 2009, rising to 72% by 2011.
In September 2012, JEDEC released the final specification of DDR4. The primary benefits of DDR4 compared to DDR3 include a higher range of clock frequencies and data transfer rates and significantly lower voltage. Intel Haswell CPUs released in 2H 2014, e.g. E5-16xx/26xx v3 server CPUs released on 9 September 2014, were among the first to use DDR4.
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JEDEC is already well along in the development of the DDR3 standard, and we have been working on it for about three years now.... Following historical models, you could reasonably expect the same three-year transition to a new technology that you have seen for the last several generations of standard memory[dead link]
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- DDR, DDR2, DDR3 memory slots testing
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