A DIMM or dual in-line memory module comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs (single in-line memory modules) as the predominant type of memory module as Intel P5-based Pentium processors began to gain market share.
While the contacts on SIMMs on both sides are redundant, DIMMs have separate electrical contacts on each side of the module. Another difference is that standard SIMMs have a 32-bit data path, while standard DIMMs have a 64-bit data path. Since Intel's Pentium many processors have a 64-bit bus width, requiring SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel. DIMMs were introduced to eliminate this practice.
The most common types of DIMMs are:
- 72-pin SO-DIMM (not the same as a 72-pin SIMM), used for FPM DRAM and EDO DRAM
- 100-pin DIMM, used for printer SDRAM
- 144-pin SO-DIMM, used for SDR SDRAM
- 168-pin DIMM, used for SDR SDRAM (less frequently for FPM/EDO DRAM in workstations/servers, may be 3.3 or 5 V)
- 172-pin MicroDIMM, used for DDR SDRAM
- 184-pin DIMM, used for DDR SDRAM
- 200-pin SO-DIMM, used for DDR SDRAM and DDR2 SDRAM
- 204-pin SO-DIMM, used for DDR3 SDRAM
- 214-pin MicroDIMM, used for DDR2 SDRAM
- 240-pin DIMM, used for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM
- 244-pin MiniDIMM, used for DDR2 SDRAM
168-pin SDRAM 
On the bottom edge of 168-pin DIMMs there are 2 notches, and the location of each notch determines a particular feature of the module.
- The first notch is DRAM key position. It represents RFU (reserved future use), registered, and unbuffered (in that order from left to middle to right position).
- The second notch is voltage key position. It represents 5.0V, 3.3V, and Reserved (order as above).
- The upper DIMM in the (topmost) photo is an unbuffered 3.3V 168-pin DIMM. DIMM slots support also DDR1, 2, 3 RAM.
DDR DIMMs 
DDR, DDR2 and DDR3 all have a different pin-counts, and different notch positions.
SPD EEPROM 
A DIMM's capacity and other operational parameters may be identified with serial presence detect (SPD), an additional chip which contains information about the module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors (TS-on-DIMM).
Error correction 
ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses an extra byte per 64-bit word. ECC modules usually carry a multiple of 9 instead of a multiple of 8 chips.
Sometimes memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank. Since all ranks share the same buses, only one rank may be accessed at any given time; it is specified by activating the corresponding rank's chip select (CS) signal. All other ranks are deactivated for the duration of the operation by having their corresponding CS signals deactivated. DIMMs are currently being commonly manufactured with up to four ranks per module. Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs.
DIMMs are often referred to as "single-sided" or "double-sided" to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board (PCB). However, these terms may cause confusion, as the physical layout of the chips does not necessarily relate to how they are logically organized or accessed.
JEDEC decided that the terms "dual-sided," "double-sided," or "dual-banked" were not correct when applied to registered DIMMs.
Most DIMMs are built using "×4" (by 4) memory chips or "×8" (by 8) memory chips with 9 chips per side. "×4" or "×8" refer to the data width of the DRAM chips in bits.
In the case of the "×4"-registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked.
For "×8"-registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).
Note: The above example applies to ECC memory which stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight which is not counted.
For various technologies, there are certain bus and device clock frequencies that are standardized. There is also a decided nomenclature for each of these speeds for each type.
SDR SDRAM DIMMs - These first synchronous registered DRAM DIMMs had the same bus frequency for data, address and control lines.
- PC66 = 66 MHz
- PC100 = 100 MHz
- PC133 = 133 MHz
DDR SDRAM (DDR1) DIMMs - DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes.
- PC1600 = 200 MHz data & strobe / 100 MHz clock for address and control
- PC2100 = 266 MHz data & strobe / 133 MHz clock for address and control
- PC2700 = 333 MHz data & strobe / 166 MHz clock for address and control
- PC3200 = 400 MHz data & strobe / 200 MHz clock for address and control
DDR2 SDRAM DIMMs - DIMMs based on Double Data Rate 2 (DDR2) DRAM also have data and data strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR2 is significantly lower than DDR(1) at the same speed.
- PC2-3200 = 400 MHz data & strobe / 200 MHz clock for address and control
- PC2-4200 = 533 MHz data & strobe / 266 MHz clock for address and control
- PC2-5300 = 667 MHz data & strobe / 333 MHz clock for address and control
- PC2-6400 = 800 MHz data & strobe / 400 MHz clock for address and control
- PC2-8500 = 1066 MHz data & strobe / 533 MHz clock for address and control
DDR3 SDRAM DIMMs - DIMMs based on Double Data Rate 3 (DDR3) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR3 is lower than DDR2 of the same speed.
- PC3-6400 = 800 MHz data & strobe / 400 MHz clock for address and control
- PC3-8500 = 1066 MHz data & strobe / 533 MHz clock for address and control
- PC3-10600 = 1333 MHz data & strobe / 667 MHz clock for address and control
- PC3-12800 = 1600 MHz data & strobe / 800 MHz clock for address and control
- PC3-14900 = 1866 MHz data & strobe / 933 MHz clock for address and control
- PC3-17000 = 2133 MHz data & strobe / 1066 MHz clock for address and control
Form factors 
Several form factors are commonly used in DIMMs. Single Data Rate (SDR) SDRAM DIMMs commonly came in two main heights: 1.7-inch and 1.5-inch. When 1U rackmount servers started becoming popular, these form factor Registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75" high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "Low Profile" (LP) height of ~1.2". These fit into vertical DIMM sockets for a 1U platform. With the advent of blade servers, the LP form factor DIMMs have once again been often angled to fit in these space-constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of ~.72" (18.3 mm). The DDR3 JEDEC standard for VLP DIMM height is 18.75mm. These will fit vertically in ATCA systems. Other DIMM form factors include the SO-DIMM, the Mini-DIMM and the VLP Mini-DIMM.
See also 
- Dual in-line package (DIP)
- Rambus in-line memory module (RIMM)
- Single in-line memory module (SIMM)
- Single in-line package (SIP)
- Zig-zag in-line package (ZIP)
- Memory Geometry
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