List of Super NES enhancement chips
As part of the overall plan for the Super Nintendo Entertainment System, rather than include an expensive CPU that would still become obsolete in a few years, the hardware designers made it easy to interface special coprocessor chips to the console. Rather than require a console upgrade, these enhancement chips were included inside the plug-in game cartridges. The presence of an enhancement chip is most often indicated by the presence of 16 additional pins on the cartridge card edge.
The Super FX chip is a 16-bit supplemental RISC CPU developed by Argonaut Games that was included in certain game cartridges to perform functions that the main CPU could not feasibly do. It was typically programmed to act as a graphics accelerator chip that would draw polygons to a frame buffer in the RAM that sat adjacent to it.
In addition to rendering polygons, the chip was also used to assist the SNES in rendering advanced 2D effects. Super Mario World 2: Yoshi's Island used it for advanced graphics effects like sprite scaling and stretching, huge sprites that allowed for boss characters to take up the whole screen, and multiple foreground and background parallax layers to give a greater illusion of depth.
This chip went through at least four revisions, first starting out as a surface mounted chip labeled MARIO CHIP 1 (Mathematical, Argonaut, Rotation & I/O) in the earliest Star Fox cartridges, commonly called the Super FX. The following year some boards were providing an epoxy version of it, and later a first revision came out under the label GSU-1. Both versions are clocked with a 21 MHz signal, but an internal clock speed divider halved it to 10.5 MHz on the MARIO CHIP 1. The GSU-1 however ran at the full 21 MHz. Both the MARIO CHIP 1 and the GSU-1 could support a ROM size of maximum 8 MBit. Later on, the design was revised to become the GSU-2, known as the Super FX 2 which was still 16bit, but unlike the earlier Super FX chips, this version could support a ROM size higher than 8 MBit. The final known revision was the GSU-2-SP1 (Service Pack 1) which probably fixed some issues or optimized the earlier revision, but the details are unknown. All versions of the Super FX chip are functionally compatible in terms of their instruction set. The differences arise in how they are packaged, their pin out, their maximum supported ROM size and their internal clock speed.
The Cx4 chip is a math coprocessor that was used by Capcom to perform general trigonometric calculations for wireframe effects, sprite positioning and rotation. It is known for its role in mapping and transforming wireframes in Capcom's second and third Mega Man X series games. It is based on the Hitachi HG51B169 DSP.
A Cx4 self-test screen can be accessed by holding the 'B' button on the second controller upon system start-up in both Mega Man X2 and Mega Man X3. In both the PlayStation 2 and Nintendo GameCube versions of Mega Man X Collection, this self-test screen is still accessible in Mega Man X2 (although differently accessed due to the remapped controller configuration), but not in Mega Man X3, because Mega Man X Collection features the 32-bit CD version of the game and not the SNES version.
This series of fixed-point digital signal processor chips allowed for fast vector-based calculations, bitmap conversions, both 2D and 3D coordinate transformations, and other functions. Four revisions of the chip exist, each physically identical but with different microcode. The DSP-1 version, including the later 1A die shrink and 1B bug fix revisions, was most often used; the DSP-2, DSP-3, and DSP-4 were used in only one title each. All of them are based on the NEC µPD77C25 CPU.
The DSP-1 is the most varied and widely used of the SNES DSPs, appearing in over 15 separate titles. It is used as a math coprocessor in games such as Super Mario Kart and Pilotwings that require more advanced Mode 7 scaling and rotation. It also provides fast support for the floating point and trigonometric calculations needed by 3D math algorithms. The later DSP-1A and DSP-1B serve the same purpose as the DSP-1. The DSP-1A was a die shrink of the DSP-1, and the DSP-1B also corrected several bugs.
The DSP-2 can only be found in the SNES port of Dungeon Master. Its primary purpose is to convert Atari ST bitmap image data into the SNES bitplane format. It also provides dynamic scaling capability and transparency effects.
Assistant chip used in only one game for the Japanese Super Famicom, a turn-based strategy game titled SD Gundam GX. The chip assisted with tasks like calculating the next AI move, Shannon-Fano bitstream decompression, and bitplane conversion of graphics.
A DSP used in only one game cartridge, Top Gear 3000. It primarily helped out with drawing the race track, especially during the times that the track branched into multiple paths.
The chip used inside the Super Game Boy peripheral possessed a core identical to the Z80-derived CPU in the handheld Game Boy. Because the Super NES was not powerful enough for software emulation of the Game Boy, circuitry equivalent to an entire handheld console had to sit inside of the cartridge.
This chip was made by MegaChips exclusively for Nintendo Power cartridges. The cartridges were equipped with flash ROMs instead of mask ROMs, and were designed to hold games downloaded from specialized kiosks for a fee. The chip managed communication with the kiosks to download ROM images, and provided an initial menu to select which of the downloaded games would be played. Some titles were available both in cartridge and download form, while others were download only. The service was closed on February 8, 2007.
The S-DD1 chip is a powerful ASIC decompressor made by Nintendo for use in some Super Nintendo Entertainment System Game Paks. Designed to handle data compressed by ABS Lossless Entropy Algorithm, a form of arithmetic coding developed by Ricoh, its use was necessary in games where massive amounts of sprite data had to be compressed with a 32-megabit data limit in mind. This data is decompressed on-the-fly by the S-DD1 and given directly to the picture processing unit.
The S-DD1 mediates between the Super NES's core CPU (the Ricoh 5A22) and the game's ROM via two buses. However, the controlling 5A22 processor may still request normal, uncompressed data from the game's ROM even if the S-DD1 is already busy with a decompression operation. This form of parallelism allows sprite data to be decompressed while other types of data are quickly passed to the main CPU.
Similar to the 5A22 CPU in the SNES console, the SA1 contains a processor core based on the 65C816 with several programmable timers. The SA1 does not function as a slave CPU for the 5A22; both can interrupt each other independently.
The SA1 also features a range of enhancements over the standard 65C816:
- Upgraded 10.74 MHz clock speed, up from a maximum of 3.58 MHz
- Faster RAM, including 2KBytes of internal RAM
- Memory mapping capabilities
- Limited data storage and compression
- New DMA modes such as bitmap to bit plane transfer
- Arithmetic functions (multiplication, division, and cumulative)
- Hardware timer (either as a linear 18-bit timer, or synchronised with the PPU to generate an IRQ at a specific H/V scanline location)
- Built-in CIC lockout, for copy protection and regional marketing control
List of Super NES games that use enhancement chips
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