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A datapath is a collection of functional units, as arithmetic logic units or multipliers, that perform data processing operations, registers, and buses.[1] Along with the control unit it composes the central processing unit (CPU).[1]

Recently, there has been growing research in the area of reconfigurable datapaths—datapaths that may be re-purposed at run-time using programmable fabric—as such designs may allow for more efficient processing as well as substantial power savings.[2]

Functional blocks of a datapath[edit]

In computer processors, the datapath often consists of the following functional blocks, or some variation thereof:

  • The instruction register stores the current instruction to be executed.
  • The program counter (PC) stores the address of the next instruction to be fetched.
  • The memory address register (MAR) is a register that either stores the memory address from which data will be fetched to the CPU or the address to which data will be sent and stored.
  • The memory data register (MDR) is a register of a computer's control unit that contains the data to be stored in the computer storage (e. g. RAM), or the data after a fetch from the computer storage.

There are also 2 registers inherent in the processor that facilitate the communication of the processor with the memory, or basically help in the memory operations of the register.

Single bus organization of datapath[edit]

The first and foremost important interconnecting medium for all the registers inside the processor is the System bus. This bus is the processor bus and is not to be confused with the external bus that connects different memory chips and I/O devices to the processor.

This external bus is connected to the internal System bus via the MAR and the MDR registers. The data lines of the external bus are connected to MDR and the address lines of the external bus are connected to the MAR. The MDR is a bidirectional register implying that it can receive and send data to and from any one of the two internal or external buses. The MAR is a unidirectional register. It receives its input from the internal bus and gives its output to the external bus.

The Arithmetic logic unit (ALU) is used for performing arithmetic and logic operations on the data contained in different registers. It is the heart of the microprocessor. The multiplexer is provided for selecting either the constant value 4 or the register X. The constant value 4 is selected when one instruction is completed and The Program Counter is to be incremented. {As mentioned before : (PC ← (PC)+4)}. The "instruction decoder and control logic" block decodes and carries out the instruction present in the IR register. The processor uses all these blocks together to carry out different primary operations such as :

  1. Inter Register data transfers
  2. Arithmetic or Logical operations
  3. Retrieving data from Memory
  4. Writing data into the Memory


Let us consider addition as an Arithmetic operation and Retrieving data from memory in detail.

Example 1) Arithmetic addition : contents of register reg1 and reg2 are added and the result is stored in reg3

Sequence of operations:

  1. reg1out,Xin
  2. reg2out,choose X,ADDITION,Yin
  3. Yout,reg3in

The control signals written in one line are executed in the same clock cycle. all other signals remain untouched. So, in the first step the contents of register1 are written into the register X through the bus. In the second stage the content of register2 is placed onto the bus and the Multiplexer is made to choose input X as the contents of reg1 are stored in register X. The ALU then adds the contents in the register X and reg2 and stores the result of the addition in the special temporary register Y. In the final step the result strored in Y is sent over to the register reg3 over the internal processor bus. Only one register can output its data onto bus in one step.[Hence steps 2 and 3 cannot be combined].[3]

Example 2) Retrieving data from memory To retrieve data from memory, the processor has to provide the address of the memory location where the required data is saved. The data stored at a particular required memory location can be either an instruction of a program or the operand of a particular executable instruction. The sequence of operations for the above operation is as follows:

  1. reg1out,MARin,,READM
  2. MDRinEX,WMC
  3. MDRout,reg2in,

A new control signal WMC has been introduced here. WMC stands for Wait for Memory operation to Complete. Generally the addressed device on the memory bus is slower than the microprocessor. Therefore,the microprocessor has to wait for the addressed device to complete its operation. This indication that the memory operation has been completed is given to the processor by the control signal WMC.

Also, as described above, the MDR is a bidirectional register i. e. it is connected to both the internal and external buses. Therefore the signal MDR has subscript inEX . The EX stands for the external bus. The signal implies that data is moved from the external memory bus into the MDR register. The remaining control signals are self-explanatory and can be understood easily as in Example 1 where MDR is the bidirectional Memory data register and MAR is the unidirectional Memory Address Register.

An entire instruction is executed[edit]

Now,let us put together the primary operations to see how a complete instruction is executed.

Consider for example the instruction:

ADD (reg3),reg1.

This instruction adds the data stored at the location pointed to by the register3 to the contents of register 1. The sequence of control signals for the aforementioned complete instruction are as follows:

  1. PCountout,MARin,READM,Choose4,ADDITION,Yin
  2. Yout,PCin,Xin,WMC
  3. MDRout,IRegin
  4. reg3out,MARin,READM
  5. reg1out,Xin,WMC
  6. MDRout,ChooseX,ADDITION,Yin
  7. Yout,reg1in,HALT

The first 3 steps written above are common to all the instructions of a microprocessor. These constitute the "Fetching of Instruction" Phase mentioned earlier. After the execution of the first three steps the instruction is loaded into the instruction register. The "instruction decoding and control circuitry" then decode the instruction and switch on all the control signals needed for steps 4 through 7. The steps 4 through 7 constitute the "Execution based on fetch instruction phase".

The content of register 3 is copied into the MAR register in step 4,which gives the address of the desired memory location and the READM instruction is executed. The contents of the other register 1 are transferred over the bus to the register X. As soon as the READM operation is completed the data at the desired memory location is made available in the MDR. The multiplexer is made to choose X over 4 . The contents of the two register are added in step 6 using the ADDITION instruction. The result of the addition is stored in the special register Y. Finally the value stored in Y is transferred to register1 over the bus in step 7.

The contents of the updated program counter are copied into the register X in step 2. Although there is no need to do this in the above program,the updated value of PC is generally stored in the register X in case of Branched Instructions to calculate the 'branch target address'

Multi-Bus Organizations of datapath[edit]

The Internal Organization of Processor discussed above was a single bus organization. It was discussed to get the basic idea. Practically,however,such single bus microprocessors are not feasible. They result in lengthy control signal sequences. Therefore,to cut down on the number of steps needed to execute an instruction a multi-bus organization can be used.

See also[edit]


  1. ^ a b The Essentials of Computer Organization and Architecture by Null & Lobur, 4e, pg 216 "All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units... connected by buses... where the timing is controlled by clocks."
  2. ^ J. R. Hauser and J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, FCCM’97, 1997, pp. 12 –21.
  3. ^ Computer Organization by Hamacher, Zaky, vranesic