Extendable instruction set computer

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The EISC (Extendable Instruction Set Computer) is a compressed code processor architecture for embedded applications. It has both the properties of RISC architecture, simplicity, and that of CISC processor, expendability. The architecture is developed by Advanced Digital Chips Inc., Seoul, Korea.<http://www.adc.co.kr>

Extendable Instruction Set[edit]

In embedded applications, code density is a golden goal since higher code density means less memory traffic and die area for embedded memory can be reduced. To improve code density, compressed code architectures have appeared such as THUMB by ARM and MIPS16 by MIPS and so on. In short, compressed code architectures have shorter length instructions for controlling the data path. Many compressed code architectures suffer from insufficient immediate operand fields.

While achieving high code density and a low memory access rate, the EISC architecture adopts a novel and terse scheme to resolve the problem of insufficient immediate operand fields of the compressed code architectures. The EISC uses an efficient fixed length 16-bit instruction set for 32-bit data processing. To resolve the problem of insufficient immediate operand fields in a concise way, EISC uses an independent instruction called load extension register (LERI), which consists of a 2-bit opcode and a 14-bit immediate value.

The LERI instruction extends the immediate field by loading an immediate value to a special register called the extension register. By using LERI instructions, the EISC architecture can make the program code more compact than the competing architectures, since the frequency of LERI instructions is less than 20% in many programs. In addition, EISC does not require instructions for switching its processor mode between the compressed instruction mode and the normal instruction mode. (For competing architectures, extra mode-changing instructions are added to use specific instructions such as MAC instructions.)

Instruction Set Architecture Family[edit]

The EISC has 16-bit, 32-bit and 64-bit instruction set architecture family. There exist SE (simple EISC) series and AE (Advanced EISC) series.

  • SE1608: 16-bit simple EISC family. 3-operand instruction set architecture. Not a compressed code architecture but it also uses LERI instruction to fully support 16-bit immediate value diretly.
  • SE3208: 32-bit simple EISC family. 3-operand instruction set architecture. 8 general purpose registers (GPRs).
  • AE32000: 32-bit Advanced EISC family for embedded microprocessing market. 2-operand instruction set architecture. 16 GPRs. It also has SIMD-DSP capability. The Newest instruction set architecture is AE32000C (AE32000-revision C).
  • AE64000: 64-bit Advanced EISC family for embedded microprocessing market especially robot and multimedia market.
Class Core Process Clock Freq. Average IPC Peak MIPS Gate Counts Power Consumption (@0.18 μm) Pipelines SIMD-DSP
SE SE1608 16-bit CPU 70 MHz@0.18 μm 8K 3 stages
SE3208 32-bit CPU 70 MHz@0.18 μm 13K 3 stages
AE AE32000C-Tiny up to 100 MHz@0.18 μm over 0.8 110 MIPS@100 MHz 26-30K under 0.15 mW/MHz 3 stages
AE32000C-Lucida up to 150 MHz@0.18 μm over 0.87 145 MIPS@130 MHz 50-88K under 0.30 mW/MHz 5 stages SIMD-DSP
AE32000C-Empress up to 300 MHz@0.13 μm over 0.78 120K under 0.38 mW/MHz 9 stages SIMD-DSP

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