Elliott 803

The Elliott 803 was a small, medium speed digital computer manufactured by the British company Elliott Brothers in the 1960s. About 250 were built and most British universities and colleges bought one.

History

The 800 series started with the 801, a one-off test machine built in 1957. The 802 was a production model but only seven were sold between 1958 and 1961. The short-lived 803A was built in 1959 and first delivered in 1960; the 803B was built in 1960 and first delivered in 1961. Elliott subsequently developed the much faster Elliott 503 computer to be software compatible.

Over 200 Elliott 803 computers were delivered to customers, at a price of about £29,000 in 1960 (Comparative cost in 2010 is £520,877 assuming an average inflation rate of 5.9% per year), the majority of sales being the 803B version (with more parallel paths internally, larger memory and hardware floating-point operations). In 2010, two complete Elliott 803 computers survive. One is owned by the Science Museum (London) but it is not on display to the public. The second one is owned by The National Museum of Computing (TNMoC) at Bletchley Park. Both machines are the subject of a Computer Conservation Society restoration and maintenance project which currently concentrates on the machine at TNMoC. Consequently this machine can regularly be seen in operation by visitors to that museum. An incomplete third Elliott 803 was found decaying in a scrap yard. Where possible, parts were removed for use as a source of spares for the machine at TNMoC.

The Elliott 803 was the computer used in ISI-609 process control system. The ISI-609 was the world's first process control system; the Elliott 803's role in this system was a data logger and it was used for this purpose at the world's first dual-purpose reactor (N-Reactor).

Hardware description

The 803 was a transistorised, bit-serial machine; the 803B had more parallel paths internally. It used ferrite core memory in 4096 or 8192 words of 40 bits, comprising 39 bits of data with parity. The CPU was housed in a single cabinet about 66 inches long, 16 inches deep and 56 inches high. Circuitry was based on printed circuit boards with the printed circuits being rather simple and most of the signalling carried on wires. There was a second cabinet about half the size used for the power supply, which was unusually based on a large nickel-cadmium battery with charger, an early form of uninterruptible power supply. A third cabinet (the same size as the power cabinet) was required to hold the extra working store on machines with 8192 word stores. There was an operator's control console, Creed teleprinter and high-speed paper tape reader and punch for input/output, using 5-track Elliott telecode code, not Baudot. Tape could be read at 500 characters per second and punched at 100 cps. The operator's console, about 60 inches long, allowed low-level instructions to be entered manually to manipulate addresses and data and could start, stop and step the machine: there was a loudspeaker (pulsed by the top bit of the instruction register) which allowed the operator to judge the status of a computation. The system required air conditioning, drawing about 3.5 kW of power in a minimal configuration.

Optional mass storage was available on an unusual magnetic tape system based on standard 35 mm film stock coated with iron oxide (manufactured by Kodak). At the time this was in use by the film industry to record sound tracks. Elliott's factory at Borehamwood was close to the Elstree film studios which explains the use of the 35mm sprocketed media. The 1000 foot reels held 4096 blocks of 64 words per block (4096 x 64 x 39 = 10,223,616 bits, or the equivalent of about 1.27Mbytes).

Another unusual feature was the use of magnetic cores not only for memory but also as logic gates. These logic cores had 1, 2 or 3 input windings, a trigger (read) and a output winding. Depending on their polarity, current pulses in the input windings could either magnetise the core or cancel each other out. The magnetised state of the core indicated the result of a boolean logic function. Two clock phases designated alpha and beta were used to trigger (reset to zero) alternate cores. A change from a one to a zero produced a pulse on the output winding. Cores which received alpha trigger pulses (alpha cores) had inputs fed from gates which were triggered on the beta phase (beta cores). Transistors were expensive at the time and each logic gate required only one to amplify the output winding pulse. However a single transistor could only drive the inputs of a small number (typically 3) other cores. If more than 3 inputs were to be driven up to two additional transistors could be driven by each core.

Instruction set

Instructions and data were based on a 39-bit word length with binary representation in 2's complement (invert and add 1 for negative) arithmetic. The instruction set operated on a single address and single accumulator register, with an additional auxiliary register for double length integer multiply and divide. Although it is believed that the single length divide and square root instructions were only enabled in 803s destined for process control applications, the one remaining operational 803 has been found to have these instructions enabled, probably because it was used by a software house to develop real time and process control applications. An instruction was composed of a 6-bit instruction (conventionally represented in octal) and a 13 bit address. This gave 64 instructions organised as 8 groups of 8 instructions. The 13 bit memory address field gave an addressable range of 8192 words. These 19-bit instructions were packed two to a word with an additional 39th bit between them, the so-called B-line or B digit. (The term is a legacy from the Ferranti Mark 1 computer, where the A-line represented the accumulator and the B-line an instruction modifier, both displayed on a Williams tube.) Setting the B digit had the effect of adding the contents of the memory address of the first instruction to the second instruction at execution time, enabling indirect addressing and other run-time instruction modifications. The bit time was 6 microseconds, jumps executed in 288 microseconds and simple arithmetic instructions in 576 microseconds. Floating point operations could take several milliseconds. IO was direct and there were no interrupts.

In the following descriptions, A and N represent the accumulator and the literal address, a and n represent the (initial) contents of the accumulator and addressed store location, and a' and n' the resultant contents.

Instruction Groups 0 - 3

These are fixed point arithmetic with 4 different combinations of operand and result destination:

Groups 0 - 3

Fn Operation a' n'	Fn Operation a' n'
00 Do nothing a n 01 Negate -a n 02 Replace & count n + 1 n 03 Collate a & n n 04 Add a + n n 05 Subtract a - n n 06 Clear zero n 07 Negate & add n - a n	10 Exchange n a 11 Exchange and negate -n a 12 Exchange and count n + 1 a 13 Write and collate a & n a 14 Write and add a + n a 15 Write and subtract a - n a 16 Write and clear zero a 17 Write, negate and add n - a a
20 Write a a 21 Write negatively a -a 22 Count in store a n + 1 23 Collate in store a a & n 24 Add into store a a + n 25 Negate store and add a a - n 26 Clear store a zero 27 Subtract from store a n - a	30 Replace n n 31 Replace and negate store n -n 32 Replace and count in store n n + 1 33 Replace and collate in store n a & n 34 Replace and add to store n a + n 35 Replace, negate store and add n a - n 36 Replace and clear store n zero 37 Replace and subtract from store n n - a

Instruction Group 4

Group 4 is conditional and unconditional jumps. Functions 40 - 43 jump to the first instruction of a pair, and 44 - 47 to the second.

Group 4

Fn Operation

40 Transfer to 1st instruction unconditionally 41 Transfer to 1st instruction if a is negative 42 Transfer to 1st instruction if a is zero 43 Transfer to 1st instruction if overflow set, and clear it 44 Transfer to 2nd instruction unconditionally 45 Transfer to 2nd instruction if a is negative 46 Transfer to 2nd instruction if a is zero 47 Transfer to 2nd instruction if overflow set, and clear it

Instruction Group 5

Group 5 is multiply, divide and shift instructions. Some of these use the 38-bit Auxiliary Register (AR - contents denoted by ar), which can be thought of as an extension of the accumulator at the least significant end. Multiplications and divisions regard a/ar as a signed fraction between -1 and one least significant bit less than +1. Despite the 803 Handbook saying "All odd functions in Group 5 clear the AR", function 57 does not clear it.

Group 5

Fn Operation

50 Arithmetic right shift a/ar N times 51 Logical right shift a N times, clear ar 52 Multiply a by n, result to a/ar 53 Multiply a by n, single length rounded result to a, clear ar 54 Arithmetic left shift a/ar N times 55 Logical left shift a N times, clear ar 56 Divide a/ar by n, single length quotient to a, clear ar 57 Copy ar to a, set sign bit zero, do NOT clear the ar

Instruction Group 6

Group 6 is floating point instructions (if a floating point unit is installed).

Floating point numbers are represented in a 39 bit word or in the accumulator as (from most to least significant end):

• a 30 bit 2's complement signed mantissa a in the range ½ ≤ a < 1 or -1 ≤ a < -½
• a 9 bit signed exponent b represented as a positive integer 0 ≤ (b+256) ≤ 511.

Zero is always represented by all 39 bits zero.

Note that the test for zero and test for negative jump instructions are equally valid for floating point.

Group 6

Fn Operation a' n'

60 Add n to a a + n n 61 Subtract n from a a - n n 62 Negate a and add n n - a n 63 Multiply a by n a * n n 64 Divide a by n a / n n 65 N = 4096: Convert fixed point integer in the accumulator to floating point 65 N < 4096: Fast left (end round) shift N mod 64 places 66 (Spare) 67 (Spare)

All these instructions clear the auxiliary register.

Instruction Group 7

Group 7 is input/output, with the exception of 73, which is used for subroutine linkage. There is a much more complete description of the Group 7 functions in the "Our Computer Heritage" link.

Group 7

Fn Operation

70 Read the keyboard number generator to the accumulator 71 Read one character from the tape reader and logically "or" it into the least significant 5 bits of the accumulator 72 Output to optional peripheral device such as the digital plotter: 73 Write the address of this instruction to location N 74 Send a character represented by N to the punch 75 Channel 2 function 76 Channel 2 function 77 Channel 2 function

Digital Plotter Control:

Instruction	Pen Motion
72 7168	No motion
72 7169	EAST
72 7170	WEST
72 7172	NORTH
72 7176	SOUTH
72 7173	NORTH EAST
72 7174	NORTH WEST
72 7177	SOUTH EAST
72 7178	SOUTH WEST
72 7184	Pen Up
72 7200	Pen Down

Entry to a subroutine at address N is normally effected by the sequence:

73 LINK : 40 N

The return address has been stored in a link location (typically the location before the start of the subroutine (e.g. N-1) )

and returns by using the sequence:

00 LINK / 40 1

Example Program

By way of an example, the following is the Initial Instructions, hard-wired into locations 0 - 3, and used for loading binary code from paper tape into memory. In accordance with the 803 convention, it is written with two instructions on each line, representing the contents of one word. The colon or slash between them represent a B digit value of zero or one respectively.

 0:  26 4 : 06 0    Clear loc'n 4; Clear A
 1:  22 4 / 16 3    Increment loc 4; Store A in loc'n (3 + content of loc'n 4) & clear A
 2:  55 5 : 71 0    Left shift A 5 times; Read tape and "or" into A
 3:  43 1 : 40 2    Jump to loc'n 1 if arith overflow; Jump to loc'n 2

There are several interesting and subtle points to note in this very simple program:

• There is no count. The inner loop (locations 2 and 3) packs 5-bit characters into the accumulator until overflow occurs. Thus a 39 bit word is formed of eight 5 bit characters. The most significant bit of the first character is discarded but must be a 1 (unless the next bit is a 1), in order to provoke arithmetic overflow (a change of the sign bit).
• The first word read is stored into location 4, and this is then used as the address into which subsequent words are stored.
• Blank leading and trailing tape is ignored since zeroes can be shifted left indefinitely without causing overflow.
• There is no provision to terminate the outer loop (inner loop plus location 1). The tape can be stopped manually, or allowed to run out through the reader (since the blank trailer is ignored). More usually, Initial Instructions are used to read a more sophisticated secondary bootstrap (T23) into the top of store. After writing to the last store location (8191) the address is allowed to wrap round to 0. Writing zero to locations 0 - 3 has no effect (since the contents of these locations are created by logic gates rather than being read from the core store), and a special value is then written to location 4. This value has 22 in the function code bits and the secondary bootstrap entry point minus 3 in the address bits. This means that the B digit has the effect of transforming the 16 (store) instruction in location 1 into a 40 (jump) instruction (16 + 22 = 40 in octal), and of adding 3 to the address bits. The net result is a jump to the entry point of the secondary bootstrap!

(In fact the data values for the wrapped-around locations 0 - 3 must be zero since counter values 8192, 8193 etc. change the B-modified second half of location 1 from a 16 to a 17 instruction, which sets a to n - a instead of clearing it, as required by the inner loop.)

Interrupts

The 803 had a little-known interrupt facility. Whilst it was not mentioned in the programming guide and was not used by any of the standard peripherals, the operation of the interrupt logic was described in the 803 hardware handbooks and the logic was shown in the 803 maintenance diagrams (Diagram 1:LB7 Gb). Interrupts were probably used mostly in conjunction with custom interfaces provided as part of ARCH real time process control systems. Since all input and output instructions could cause the 803 to become "busy" if input data was not available or if an output device had not completed a previous operation, interrupts were not needed and not used for driving the standard peripherals.

Raising the interrupt input to the computer would cause a break in execution as follows, as soon as the machine was in a suitable state (in particular, when not "busy" and only in certain states of the fetch/execute cycle). The next instruction pair would be fetched from store location 5, without changing the Sequence Control Register (SCR). Location 5 would be expected to contain a standard subroutine entry instruction pair (73 LINK : 40 N - see above), allowing the pre-interrupt execution address (still in the SCR) to be saved for later return. The external equipment raising the interrupt was relied upon to refrain from raising another interrupt until the first had been acknowledged by some suitable input/output instruction, so as to prevent interrupts from being nested. Interestingly, the Algol compiler did not regard location 5 as a reserved location, although this may have more to do with the unsuitability of Algol for process control applications than indicating that interrupts were never regarded as a mainstream facility.

Compilers

The Initial Instructions described as the Example Program above was effectively a primary bootloader which would normally be used to read a secondary bootloader known as T23, prepended to all program tapes. T23 allowed more flexible program loading facilities including sumchecking of the loaded code.

Machine code programs were written in an octal/decimal representation exemplified in the Example Program above, and loaded by a rudimentary assembler known as the Translation Input Routine. It had no symbolic addressing facilities, but instead allowed the source to be broken into blocks which could be manually relocated to allow for the expansion or contraction of a previous block in development. There was also an Autocode for simple programming tasks, allowing faster program development without the need for a knowledge of machine code. This had no formula translation facilities and required all calculations to be reduced to a series of assignments with no more than a single operator on the right hand side.

The 803B with 8192 words of memory was capable of running the Elliott ALGOL compiler , a major subset of the Algol60 language, capable of loading and running several ALGOL programs in succession. This was largely written by Tony Hoare, employed by Elliotts as a programmer in August 1960. Hoare recounts some of his experiences at Elliotts in his 1980 ACM Turing Award lecture.

The 803B at The National Museum of Computing is now working well enough to run this compiler again. There is a short video on YouTube of it compiling and running a simple program.

Applications

The following users are all listed in

• RMIT Melbourne utilised an Elliott 803 Computer for student use in 1966.
• Brush Electrical Machines in Loughborough UK used an 803 for design calculation on power transformers and motors.
• G.P.O. used an 803 at their Dollis Hill Research Labs for electronics design and telephone network simualtions.
• G.P.O. used an 803 at their Goonhiily Downs satellite earth station for calculating satellite passes and punching tapes to steer dishes.
• Corah Knitware in Leicester UK used a pair of 803s for telephone order processing and production planning.
• Thornber Farms in West Yorkshire UK used an 803 to process egg production data for breeding of chickens.

References

• Adrian Johnstone, The Young person's Guide to... The Elliott 803B, Resurrection (Bulletin of the Computer Conservation Society) 1 (Spring 1991) [1]
• Tony Hoare, The Emperor's Old Clothes, Communications of the ACM 24 (February 1981)
• Elliott Brothers (London) Ltd., Scientific Computing Division, A Guide to Programming the 803 Electronic Digital Computer (June 1962)
• Pathe News Reel, SCIENCE AND THE EGG, [2]

External links

• Our Computer Heritage pilot study
• Description of Initial Instructions
• An Elliott 803 emulator