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The Emotion Engine is a CPU developed and manufactured by Sony Computer Entertainment and Toshiba for use in the Sony PlayStation 2 video game console, as well as early PlayStation 3 models sold in Japan and North America (Model Numbers CECHAxx & CECHBxx). Mass production of the Emotion Engine began in 1999.
The Emotion Engine consists of eight separate "units", each performing a specific task, integrated onto the same die. These units are: a CPU core, two Vector Processing Units (VPU), a graphics interface (GIF), a 10 channel DMA unit, a memory controller, an Image Processing Unit (IPU) and an input output interface.
The CPU core is tightly coupled to the first VPU, VPU0. Together, they are responsible for executing game code and high-level modeling computations. The second VPU, VPU1, is dedicated to geometry-transformations and lighting and operates independently, parallel to the CPU core, controlled by microcode. VPU0, when not utilized, can also be used for geometry-transformations. Display lists generated are sent to the GIF, which prioritizes them before dispatching them to the Graphics Synthesizer for rendering.
CPU core 
The CPU core is a two-way superscalar in-order RISC processor. It implements the MIPS-III instruction set architecture (ISA) and much of MIPS-IV in addition to a custom 128-bit single instruction multiple data (SIMD) instruction set developed by Sony. The custom instruction set consists of 107 instructions for operating on four 32-bit, eight 16-bit or sixteen 8-bit integers simultaneously. Instructions defined include: add, subtract, multiply, divide, min/max, shift, logical, leading-zero count, 128-bit load/store and 256-bit to 128-bit funnel shift in addition to some not described by Sony for competitive reasons.
The MIPS-based core consists of two arithmetic logic units (ALUs) and a floating point unit (FPU). The integer units are 64-bit, but the FPU was single-precision, or 32-bit. The custom instruction set was implemented by grouping the two 64-bit integer units. Both the integer and floating-point pipelines are both six stages long. To support the custom instruction set, the integer registers are 128 bits wide.
To feed the execution units with instructions and data, there is a 16 KB two-way set associative instruction cache, an 8 KB two-way set associative non blocking data cache and a 16 KB scratchpad RAM. Both the instruction and data caches are virtually indexed and physically tagged while the scratchpad RAM exists in a separate memory space. A combined 48 double entry instruction and data translation lookaside buffer is provided for translating virtual addresses. Branch prediction is achieved by a 64-entry branch target address cache and a branch history table that is integrated into the instruction cache. The branch mispredict penalty is three cycles due to the short six stage pipeline.
Vector processing units 
The majority of the Emotion Engine's floating point performance is provided by two vector processing units (VPU), designated VPU0 and VPU1. Each VPU features 32 128-bit registers, 16 16-bit fixed-point registers, four FMAC (Floating point Multiply-ACcumulate) units, an FDIV (Floating point DIVide) unit and a local data memory. The data memory for VPU0 is 4 KB in size, while VPU1 features a 16 KB data memory.
To achieve high bandwidth, the VPU's data memory is connected directly to the GIF, and both of the data memories can be read directly by the DMA unit. A single vector instruction consists of four 32-bit single-precision floating-point values which are distributed to the four single-precision (32-bit) FMAC units for processing. Contrary to popular belief, the Emotion Engine is not a 128-bit processor as it does not process a single 128-bit value, but a group of four 32-bit values that are stored in one 128-bit register. This scheme is similar to the SSEx extensions by Intel.
The FMAC units take four cycles to execute one instruction, but as the units have a six-stage pipeline, they have a throughput of one instruction per cycle. The FDIV unit has a nine-stage pipeline and can execute one instruction every seven cycles.
Internal data bus 
Communications between the MIPS core, the two VPUs, GIF, memory controller and other units is handled by a 128-bit wide internal data bus running at half the clock frequency of the Emotion Engine. At 300 MHz, the internal data bus provides a maximum theoretical bandwidth of 2.4 GB/s. DMA transfers over this bus occurs in packets of eight 128-bit words, achieving a peak usable bandwidth of 2 GB/s.
External interface 
Communication between the Emotion Engine and RAM occurs through two channels of DRDRAM (Direct Rambus Dynamic Random Access Memory) and the memory controller, which interfaces to the internal data bus. Each channel is 16 bits wide and operates at 400 MHz. Combined, the two channels of DRDRAM have a maximum theoretical bandwidth of 3.2 GB/s, about 33% more bandwidth than the internal data bus. Because of this, the memory controller buffers data sent from the DRDRAM channels so the extra bandwidth can be utilised by the CPU.
The Emotion Engine interfaces directly to the Graphics Synthesizer via the GIF with a dedicated 64-bit, 150 MHz bus that has a maximum theoretical bandwidth of 1.2 GB/s.
To provide communications between the Emotion Engine and the Input Output Processor (IOP), the input output interface interfaces a 32-bit wide, 37.5 MHz input output bus with a maximum theoretical bandwidth of 150 MB/s to the internal data bus. This interface provides vastly more bandwidth than what is required by the PlayStation's input output devices.
The Emotion Engine contained 10.5 million transistors on a die measuring 240 mm2. It was fabricated by Sony and Toshiba in a 0.25 µm (0.18 µm effective LG) complementary metal–oxide–semiconductor (CMOS) process with four levels of interconnect.
The Emotion Engine was packaged in a 540-contact plastic ball grid array (PBGA).
The primary use of the Emotion Engine was to serve as the PlayStation 2's CPU. The first SKUs of the PlayStation 3 also featured an Emotion Engine on the motherboard to achieve backwards compatibility with PlayStation 2 games. However, the second revision of the PlayStation 3 lacked a physical Emotion Engine in order to lower costs, performing all of its functions using software emulation performed by the Cell Broadband Processor, coupled with a hardware Graphics Synthesizer still present to achieve PlayStation 2 backwards compatibility. In all subsequent revisions, the Graphics Synthesizer was removed, with no software emulation to replace it.
- Clock frequency: 294 MHz, 299 MHz (later versions)
- Instruction set: MIPS III, MIPS IV subset, 107 vector instructions
- MIPS based core: 2 issue, 2 64-bit fixed point units, 1 floating point unit, 6 stage pipeline
- Instruction cache: 16 KB, 2-way set associative
- Data cache: 8 KB, 2-way set associative
- Scratchpad RAM: 16 KB
- Translation look aside buffer: 48-entry combined instruction/data
- Vector processing unit: 4 FMAC units, 1 FDIV unit
- Vector processing unit registers: 128-bit wide, 32 entries
- Image processing unit: MPEG2 macroblock layer decoder
- Direct memory access: 10 channels
- VDD Voltage: 1.8 V
- Power consumption: 15 W at 1.8 V
Theoretical performance 
- Floating point: 6.2 billion single precision (32-bit) floating point operations per second
- Perspective transformation: 66 million polygons per second
- With lighting and fog: 36 million polygons per second
- Bézier surface patches: 16 million polygons per second
- Image decompression: 150 million pixels per second
- Transistorized memory, such as RAM, ROM, flash and cache sizes as well as file sizes are specified using binary meanings for K (10241), M (10242), G (10243), ...
- Hennessy, Patterson 2003, p. ?
- Diefendorff 1999, p. 3
- Disk-based memory (hard drives), solid state disk devices such as USB drives, DVD-based storage, bit rates, bus speeds, and network speeds, are specified using decimal meanings for K (10001), M (10002), G (10003), ...
- Diefendorff 1999, p. 4
- Diefendorff 1999, p. 5
See also 
- Graphics card
- Graphics processing unit
- Computer graphics
- List of computer graphics and descriptive geometry topics
- Hennessy, John L.; Patterson, David A. (29 May 2002). Computer Architecture: A Quantitative Approach (3 ed.). Morgan Kaufmann. ISBN 978-0-08-050252-6. Retrieved 9 April 2013.
- Diefendorff, Keith (19 April 1999). "Sony's Emotionally Charged Chip". Microprocessor Report (Microdesign Resources) 13 (5).