Esterel Studio

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Esterel Studio is a design environment based on the Esterel language. It is optimized for hardware IPs (such as DMAs, protocols, cache controllers, I/O subsystems, etc.) dedicated at capturing formal design specifications, enabling formal verification of properties early in the design phase, and automating the production of synthesizable RTL (VHDL and Verilog), both for prototyping and production purposes.

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