Front end of line
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The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.
FEOL contains all processes of CMOS fabrication needed to form fully isolated CMOS elements:
- Selecting the type of wafer to be used; Chemical-mechanical planarization and cleaning of the wafer.
- Shallow trench isolation (STI) (or LOCOS in early processes, with feature size > 0.25 μm)
- Well formation
- Gate module formation
- Source and drain module formation
[edit] References
- ^ Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 9780815515548. http://books.google.com/books?id=UPaD8JUCKr0C&pg=PA202.
[edit] Further reading
- "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)
[edit] See also
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