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The processor itself had no address bus — memory addresses were kept in each co-processor's own address counter and was manipulated through five control signals, reducing the number of pins and the associated cost. It also featured 64 bytes of scratchpad memory, accessed by the ISAR register in cells (register windows) of eight, which meant external RAM was not always needed for small applications. In addition, the 2-chip processor did not need support chips, unlike others which needed seven or more.
The use of the ISAR register allowed a subroutine to be entered without saving registers, the ISAR would just be changed, speeding execution. Special purpose registers were usually stored in the second cell (regs 8-15), and only the first sixteen registers could be accessed directly. The windowing concept was useful, but only the register pointed to by the ISAR could be accessed — to access other registers, the ISAR was incremented or decremented through the window.
The F8 ran at 1 MHz-2 MHz, yielding a 0.5 μs cycle time.
- Datasheet: http://datasheets.chipdb.org/Fairchild/F8/fairchild-3850.pdf
- Patent: http://www.google.com/patents/US4086626
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