Summary

Description2-bit ALU.png	English: A simple example arithmetic logic unit (ALU) that does AND, OR, XOR, and addition. Español: Un ejemplo sencillo de una Unidad Aritmética Lógica (ALU) que realiza operaciones AND, OR, XOR, y adición. Eesti: Näidis aritmeerika-loogikaplokk mis teeb AND, OR, XOR ja liitmise opratsioone
Date	16 November 2006
Source	English: Own work created with Eagle by Cadsoft Español: Trabajo hecho bajo Eagle por Cadsoft Eesti: Üleslaadija oma töö, tehtud Cadsofti Eagle'iga
Author	en:User:Cburnett
Permission (Reusing this file)	Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled GNU Free Documentation License.http://www.gnu.org/copyleft/fdl.htmlGFDLGNU Free Documentation Licensetruetrue This file is licensed under the Creative Commons Attribution-Share Alike 3.0 Unported license. You are free: to share – to copy, distribute and transmit the work to remix – to adapt the work Under the following conditions: attribution – You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use. share alike – If you remix, transform, or build upon the material, you must distribute your contributions under the same or compatible license as the original. This licensing tag was added to this file as part of the GFDL licensing update.http://creativecommons.org/licenses/by-sa/3.0/CC BY-SA 3.0Creative Commons Attribution-Share Alike 3.0truetrue
Other versions	File:2-bit ALU.svg is a vector version of this file. It should be used in place of this PNG file when not inferior. File:2-bit ALU.png → File:2-bit ALU.svg For more information, see Help:SVG. In other languages Alemannisch ∙ Bahasa Indonesia ∙ Bahasa Melayu ∙ British English ∙ català ∙ čeština ∙ dansk ∙ Deutsch ∙ eesti ∙ English ∙ español ∙ Esperanto ∙ euskara ∙ français ∙ Frysk ∙ galego ∙ hrvatski ∙ Ido ∙ italiano ∙ lietuvių ∙ magyar ∙ Nederlands ∙ norsk bokmål ∙ norsk nynorsk ∙ occitan ∙ Plattdüütsch ∙ polski ∙ português ∙ português do Brasil ∙ română ∙ Scots ∙ sicilianu ∙ slovenčina ∙ slovenščina ∙ suomi ∙ svenska ∙ Tiếng Việt ∙ Türkçe ∙ vèneto ∙ Ελληνικά ∙ беларуская (тарашкевіца) ∙ български ∙ македонски ∙ нохчийн ∙ русский ∙ српски / srpski ∙ татарча/tatarça ∙ українська ∙ ქართული ∙ հայերեն ∙ বাংলা ∙ தமிழ் ∙ മലയാളം ∙ ไทย ∙ 한국어 ∙ 日本語 ∙ 简体中文 ∙ 繁體中文 ∙ עברית ∙ العربية ∙ فارسی ∙ +/−

EN

This ALU is a 2-bit ALU with two inputs (operands) named A and B: A[0] & B[0] are the least-significant bits and A[1] & B[1] are the most-significant bits.

Each bit of this ALU is identical with the exception of the handling of the carry bit. The handling of one bit is explained below.

The A & B inputs lead into the four gates on the left (from top to bottom): XOR, AND, OR, and XOR. The top three gates perform XOR, AND, and OR operations on A & B. The last gate is the initial gate into a full adder.

The final step to each bit is the multiplexer at the end. The 3-bit OP input (from the control unit) determines which of the functions is outputted:

• OP = 000 → XOR
• OP = 001 → AND
• OP = 010 → OR
• OP = 011 → Addition

Clearly, the last four inputs of the multiplexer are free for other functions (subtraction, multiplication, division, NOT A, NOT B, etc.). Although OP[2] is not currently used (though it is included and connected), it will be needed in order to use more than the 4 operations listed above.

Ted flags, are typically connected to some form of a status register.

ES

Esta ALU es una ALU de 2-bits con dos entradas (operandos) llamadas A y B: A[0] y B[0] corresponden al bit menos significativo y A[1] y B[1] corresponden al bit más significativo.

Cada bit de esta ALU es idéntico con la excepción del direccionamiento del bit del acarreo. El manejo de este bit es explicado más adelante.

Las entradas A y B van hacia las cuatro puertas de la izquierda (de arriba a abajo): XOR, AND, OR, y XOR. Las tres primeras puertas realizan las operaciones XOR, AND, y OR sobre los datos A y B. La última puerta es la puerta inicial de un sumador completo.

El paso final de las operaciones sobre cada bit es la multiplexación de los datos. La entrada OP de 3-bits (desde la unidad de control) determina cual de las funciones se van a realizar:

• OP = 000 → XOR
• OP = 001 → AND
• OP = 010 → OR
• OP = 011 → Adición

Claramente se ve que las otras cuatro entradas del multiplexor están libres para otras operaciones (sustracción, multiplicación, división, NOT A, NOT B, etc.). Aunque OP[2] actualmente no es usada en este montaje (a pesar de estar incluída y conectada), ésta sería usada en el momento de realizar otras operaciones además de las 4 operaciones listadas arriba.

Los datos de acarreo de entrada y acarreo de salida, llamados flags (banderas), son típicamente conectados a algún tipo de registro de estado.

ET

See ALU on 2-bitine ALU, millel on 2 sisendit A ja B: A[0] & B[0] on vähima kaaluga bitt ja A[1] & B[1] suurima kaaluga bit. Iga ALU bitt peale ülekandebiti on identsed.

A & B sisendid ühendavad 4 elementi vasakul (ülevalt alla): XOR, AND, OR, ja XOR. 3 ülemist elementi teostavad XOR, AND ja OR operatsioone A & B peal. Viimane element on algne element summatorile.

Iga biti viimane samm on multiplekser lõpus. 3-bitine OP sisend (kontrollblokist)määrab, milline funktsioon läheb väljundisse :

• OP = 000 → XOR
• OP = 001 → AND
• OP = 010 → OR
• OP = 011 → Liitmine

Multiplekseri 4 viimast sisendit on vabad muude operatsioonide jaoks (lahutamine, korrutamine, jagamine, NOT A, NOT B, jne). Kuigi OP[2] ei kasutata (kuigi see on ühendatud ja skeemis olemas) läheb seda vaja täiendavate funktsioonide kasutamiseks kui eelpool ära toodud.

Ülekandebitid on tüüpiliselt ühendatud mingisuguse olekuregistriga.

Licensing

I, the copyright holder of this work, hereby publish it under the following license:

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled GNU Free Documentation License.http://www.gnu.org/copyleft/fdl.htmlGFDLGNU Free Documentation Licensetruetrue

	This file is licensed under the Creative Commons Attribution-Share Alike 3.0 Unported license.
	You are free: to share – to copy, distribute and transmit the work to remix – to adapt the work Under the following conditions: attribution – You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use. share alike – If you remix, transform, or build upon the material, you must distribute your contributions under the same or compatible license as the original.
	This licensing tag was added to this file as part of the GFDL licensing update.http://creativecommons.org/licenses/by-sa/3.0/CC BY-SA 3.0Creative Commons Attribution-Share Alike 3.0truetrue