A 7nm node metal layer can be patterned by two masks with the Spacer-is-Dielectric (SID) approach. Here the blue pattern indicates the core pattern defined by a first mask, while the red locations are where the spacer gap-fill material is deposited following the spacer patterning (not shown). The yellow pattern is the block pattern defined by the second mask, to complete the overall pattern. Ref.: US Patent 8312494, assigned to Synopsys.
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