File:CMOS NAND Layout.svg
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This is a file from the Wikimedia Commons. Information from its description page there is shown below. |
| Description |
English: The physical layout of a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup. The physical layout of a CMOS NAND.
עברית: שער לוגי מסוג NAND ממבט על.
Polski: budowa bramki NAND CMOS.
Română: Aranjamentul fizic al unei porţi NAND CMOS.
中文: CMOS与非门的布图.
CMOS NAND Layout for chip |
| Date | 2006-09-07 (first version); 2006-09-07 (last version) |
| Source | Originally from en.wikipedia; description page is/was here. |
| Author | Original uploader was Jamesm76 at en.wikipedia |
| Permission (Reusing this file) |
Released into the public domain (by the author). |
| Other versions |
Derivative works of this file: |
[edit] Licensing
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This work has been released into the public domain by its author, Jamesm76 at the wikipedia project. This applies worldwide. In case this is not legally possible:
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[edit] Original upload log
(All user names refer to en.wikipedia)
- 2006-09-07 23:46 Jamesm76 294×587×0 (11839 bytes) I am the author and I release this to the public domain.
- 2006-09-07 23:27 Jamesm76 294×587×0 (11827 bytes) SVG drawing of a CMOS NAND gate replacing the older PNG version I had previously uploaded ("CMOS NAND Layout.png"). I am the author and I release this to the public domain.
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 20:46, 19 October 2007 | | 294 × 587 (12 KB) | Prolineserver | {{Information |Description=''no original description'' |Source=Originally from [http://en.wikipedia.org en.wikipedia]; description page is/was [http://en.wikipedia.org/w/index.php?title=Image%3ACMOS_NAND_Layout.svg here]. |Date=2006-09-07 (first version); |
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