GDDR5, an abbreviation for double data rate type five synchronous graphics random access memory, is a modern type of synchronous graphics random access memory (SGRAM) with a high bandwidth ("double data rate") interface designed for use in graphics cards, game consoles, and high-performance computation.
GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by the JEDEC. SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other VRAM technologies. It uses an 8n-prefetch architecture and DDR interface to achieve high performance operation and can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization. The GDDR5 interface transfers two 32-bit wide data words per write clock (WCK) cycle to/from the I/O pins. Corresponding to the 8n-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.
GDDR5 operates with two different clock types. A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes, that runs at twice the CK frequency. Being more precise, the GDDR5 SGRAM uses a total of three clocks: two write clocks associated with two bytes (WCK01 and WCK23) and a single command clock (CK). Taking a GDDR5 with 5 Gbit/s data rate per pin as an example, the CK clock runs with 1.25 GHz and both WCK clocks at 2.5 GHz. The CK and WCKs are phase aligned during the initialization and training sequence. This alignment allows read and write access with minimum latency.
A single 32-bit GDDR5 chip has about 67 signal pins and the rest are power and grounds in the 170 BGA package.
In 2007, Qimonda, a spin-off of Infineon, demonstrated and sampled GDDR5, and released a paper about the technologies behind GDDR5. As of May 10, 2008, Qimonda announced volume production of 512 MB GDDR5 modules rated at 3.6 Gbps (900 MHz), 4.0 Gbps (1 GHz), and 4.5 Gbps (1.125 GHz).
Hynix Semiconductor introduced the industry's first 60nm class 1 Gb GDDR5 memory in 2007. It supported a bandwidth of 20 GB/s on a 32-bit bus, which enables memory configurations of 1 GB at 160 GB/s with only 8 circuits on a 256-bit bus. The following year, in 2008, Hynix bested this technology with its 50nm class 1 Gb GDDR5 memory. Hynix 40nm class 2 Gb GDDR5 was released in 2010. It operates at 7 GHz effective clock-speed and processes up to 28 GB/s. 2 Gb GDDR5 memory chips will enable graphics cards with 2 GB or more of onboard memory with 224 GB/s or higher peak bandwidth. 4 Gb density GDDR5 modules first starting becoming available in the third quarter of 2013. Initially released by Hynix, Micron Technology quickly followed up with their implementation releasing in 2014. Modules from both Micron and Hynix, of both the 2 Gb and 4 Gb densities, range in bit rate up to 7 Gbps.
On June 25, 2008, AMD became the first company to ship products using GDDR5 memory with its Radeon HD 4870 video card series, incorporating Qimonda's 512 MB memory modules at 3.6 Gbps bandwidth.
On February 20, 2013, it was announced that the PlayStation 4 will use sixteen 4 Gb (i.e. sixteen 512 MB) GDDR5 memory chips for 8 GB of GDDR5 @ 176 Gbps (CK 1.375 GHz and WCK 2.75 GHz) as combined system and graphics RAM for use with its AMD-powered System on a chip comprising 8 Jaguar cores, 1152 GCN shader processors and AMD TrueAudio.
As of January 15, 2015, Samsung Electronics announced in a press release that it had begun mass production of 8 Gb density GDDR5 memory chips based on a 20nm fabrication process. To meet the demand of higher resolution displays (such as 4K) becoming more mainstream, higher density chips are required in order to facilitate larger frame buffers for graphically intensive computation, namely PC gaming and other 3D rendering. Increased bandwidth of the new high-density modules equates to 8 Gbps per pin x 170 pins on the BGA package x 32-bits per I/O cycle, or 256 Gbps effective bandwidth per chip. 
- Micron TN-ED-01: GDDR5 SGRAM Introduction. Accessed April 11, 2014
- Register report. Retrieved November 2, 2007.
- Qimonda GDDR5 White Paper
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- Hynix 1H '11 Product Catalog, page 8. Accessed July 24, 2014.
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- Micron: 2gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN., retrieved July 24, 2014
- Hynix: Q2 '13 Databook, page 2., retrieved July 24, 2014
- Hynix: 4gb_gddr5_sgram_brief.pdf - Rev. A 2/14 EN., retrieved July 24, 2014
- Qimonda Press Release[dead link]. May 21, 2008
- AMD Press Release. June 25, 2008
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- Introduction To GDDR5 SGRAM(by ELPIDA)
- Making Accurate Measurements on GDDR5 Memory Systems
- GDDR5 Pinout and Description