Gekko (microprocessor)

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Gekko
GEKKO.jpg
IBM Gekko processor
Produced From 2000 to 2007
Designed by IBM and Nintendo
Common manufacturer(s)
Max. CPU clock rate 486 MHz 
Min. feature size 180 nm
Instruction set Power Architecture
Microarchitecture PowerPC ISA 1.10
Cores 1
L1 cache 32/32 kB
L2 cache 256 kB
Application Nintendo GameCube
Predecessor NEC VR4300
Successor Broadway
Variant

Gekko is a 32-bit PowerPC microprocessor custom made by IBM in 2000 for Nintendo to use as the CPU in their sixth generation game console, the Nintendo GameCube.

Development[edit]

Gekko's role in the game system was to facilitate game scripting, artificial intelligence, physics and collision detection, custom graphics lighting effects and geometry such as smooth transformations, and moving graphics data through the system.

The project was announced in 1999 when IBM and Nintendo agreed to a one billion dollar contract for a CPU running at approximately 400 MHz. IBM chose to modify their existing PowerPC 750CXe processor to suit Nintendo's needs, such as tight and balanced operation alongside the "Flipper" graphics processor. The customization was to the bus architecture, DMA, compression and floating point unit which support a special set of SIMD instructions. The CPU made ground work for custom lighting and geometry effects and could burst compressed data directly to the GPU.

IBM's customization led to performance that exceeded Nintendo's specifications.[citation needed] The Gekko is considered to be the direct ancestor to the Broadway processor, also designed and manufactured by IBM, that powers the Wii console.

Features[edit]

  • Customized PowerPC 750CXe core
  • Clockrate - 486 MHz
  • Integer unit - 32 bit
  • Floating Point Unit - 64-bit double precision FPU, usable as 2×32-bit SIMD for 1.9 single-precision GFLOPS performance, often found under the denomination "paired singles"
  • SIMD Instructions - PowerPC750 + Roughly 50 new SIMD instructions, geared toward 3D graphics
  • Front-side Bus - 64-bit enhanced 60x bus to GPU/chipset at 162 MHz clock with 1.3 GB/s peak bandwidth
  • On-chip Cache - 64 kB 8-way associative L1 cache (32/32 kB instruction/data). 256 KB on-die, 2-way associative L2 cache
  • DMIPS - 1125 (dhrystone 2.1)
  • 180 nm IBM six layer, copper-wire process. 43 mm² die
  • 1.8 V for logic and I/O. 4.9 W dissipation
  • 27×27 mm PBGA package with 256 contacts
  • 6.35 million logic transistors and 18.6 million transistors total

See also[edit]

References[edit]