Halt and Catch Fire
Halt and Catch Fire, known by the assembly mnemonic HCF, refers to several computer machine code instructions that cause a computer's CPU to cease meaningful operation. The expression "catch fire" is intended as a joke; the CPU does not literally catch fire, but it does stop functioning. It is also occasionally referred to as "SDI" for "Self Destruct Immediate".
In early CPUs
In a computer's assembly language, mnemonics are used that are directly equivalent to machine code instructions. The mnemonics are frequently three letters long, such as ADD, CMP (to compare two numbers), and JMP (jump to a different location in the program). The HCF instruction was originally a fictitious assembly language instruction, said to be under development at IBM for use in their System/360 computers, along with many other amusing instructions like XPR (Execute Programmer) and CAI (Corrupt Accounting Information). The S/360 instruction set already included numerous complex and non-obvious operations like ZAP (Zero and Add Packed), EDMK (EDit and MarK), TRT (TRanslate and Test), and Read Backward (an I/O channel command), so programmers humorously proposed creating more like them.
One apocryphal story about the HCF instruction goes back to the late 1960s, when computers used magnetic core memory. The story goes that in order to speed up the core memory on their next model the engineers increased the read/write currents in the very fine wires that were threaded through the cores. This worked fine when the computer was executing normal programs, since memory accesses were spread throughout memory. However, the HALT instruction was implemented as a "Jump to self". This meant that the same core memory location was repeatedly accessed, and the very fine wires became so hot that they started to smoke — hence the instruction was labeled "Halt and Catch Fire".
In modern CPUs
CPU designers sometimes incorporate one or more undocumented machine code instructions for testing purposes. These instructions are not intended to be executed during normal operation of the CPU and when they are actually executed by a program, they often have unusual side-effects.
The old "Halt and Catch Fire" instruction and HCF mnemonic are sometimes appropriated by users who discover these instructions as a humorous way of expressing that the unintended execution of such an instruction causes the system to fail to perform its normal functions.
The Motorola 6800 microprocessor was the first for which an HCF opcode became widely known. The 6800 HCF opcodes are $9D and $DD and were reported in an article written by Gerry Wheeler in the December 1977 issue of BYTE magazine on undocumented opcodes.
The opcode makes the processor enter a mode in which it continuously performs memory read cycles from successive addresses, with no intervening instruction fetches. The address bus effectively becomes a counter, allowing the operation of all address lines to be quickly verified. Once the processor has entered this mode, it is not responsive to interrupts, so normal operation can only be restored by a reset. Some engineers began referring to the operation as "Halt and Catch Fire". It has been claimed that in some hardware configurations, the unrelenting driving of the address lines caused them to smoke or burn. It is likely that the term "catch fire" is intended more as a metaphor for the unresponsive behavior of the CPU when placed in this state; there are no known examples of erratic behavior.
The HCF opcode is believed to be the first built-in self-test feature on a Motorola microprocessor.
The Intel 8086 and subsequent processors in the x86 series had an HLT (halt) instruction, op code F4, which stopped instruction execution and placed the processor in a HALT state. An enabled interrupt, a debug exception, the BINIT signal, the INIT signal, or the RESET signal resumed execution, which meant the processor could always be restarted. Some of the early IntelDX4 chips had a problem with the HLT instruction, and could not be restarted after this instruction was used, which disabled the computer and turned HLT into more of an HCF instruction. The Linux kernel added a 'no-hlt' option telling Linux to run an infinite loop instead of using HLT, which allowed users of these broken chips to use Linux.
Many computers in the Intel Pentium line could be locked up by executing an invalid instruction (F00F C7C8) which caused the computer to try to execute the invalid F00F instruction and then lock up. This became known as the Pentium F00F bug. No compiler would create the instruction, but hackers could insert it in code through devious means to crash file and communications servers. Since its discovery, workarounds have been developed to prevent it from locking the computer, and the bug has been fixed in subsequent Intel processors.
- A Proposed Instruction Set, Ohio State University, retrieved 2014-07-02
- IBM System/360 Principles of Operation, IBM, retrieved 2014-07-02
- http://catless.ncl.ac.uk/Risks/5.6.html#subj2.4 | RISKS Digest: Hardware vs Software Battles (from Usenet)
- Wheeler, Gerry (December 1977). "Undocumented M6800 Instructions". BYTE 2 (12): 46–47.
- Banks, Walter. "Mailing list entry". Retrieved 2014-06-08.
- Agans, David J. (2002). Debugging: the 9 indispensable rules for finding even the most elusive software and hardware problems. New York: American Management Association. p. 77. ISBN 9780814426784. OCLC 52043345. Retrieved July 10, 2014.
- "The Jargon File, v 3.1.0". 15 October 1994. Retrieved 2010-07-08.
- Daniels, R. Gary; Bruce, William (April 1985). "Built-In Self-Test Trends in Motorola Microprocessors". IEEE Design & Test 2 (2): pp. 64–71. doi:10.1109/MDT.1985.294865. "HACOF thus became the first intentional built-in self-test feature on a Motorola microprocessor."
- [dead link]
- "x86 Instruction Set Reference: HLT". Retrieved 2014-07-02.
- Gortmaker, Paul (March 21, 2003). "The Linux Boot Prompt-How To". The Linux Documentation Project. Retrieved 2014-07-02.
- Collins, Robert R. (May 1, 1998). "The Pentium F00F Bug: Workarounds for a nasty problem". Dr. Dobb's Journal.
- Pentium Processor Specification Update (PDF). Intel Corporation. January 1999. pp. 51–52. order number 242480-041. Retrieved 2006-11-02.