High-performance reconfigurable computing

From Wikipedia, the free encyclopedia
Jump to: navigation, search

High-Performance Reconfigurable Computing (HPRC) is a computer architecture combining reconfigurable computing-based accelerators like field-programmable gate arrays (FPGAs) with CPUs, manycore microprocessors, or other parallel computing systems. This heterogeneous systems technique is used in computing research and especially in supercomputing.[1] A 2008 paper reported speed-up factors of more than 4 orders of magnitude and energy saving factors by up to almost 4 orders of magnitude.[2] Some supercomputer firms offer heterogeneous processing blocks including FPGAs as accelerators.[citation needed] One research area is the twin-paradigm programming tool flow productivity obtained for such heterogeneous systems.[3] The US National Science Foundation has a center for high-performance reconfigurable computing (CHREC).[4] In April 2011 the fourth Many-core and Reconfigurable Supercomputing Conference was held in Europe.[5]


  1. ^ N. Voros, R. Nikolaos, A. Rosti, M. Hübner (editors): Dynamic System Reconfiguration in Heterogeneous Platforms - The MORPHEUS Approach; Springer Verlag, 2009
  2. ^ Tarek El-Ghazawi et al. (February 2008). "The promise of high-performance reconfigurable computing". IEEE Computer 41 (2): 69–76. doi:10.1109/MC.2008.65. 
  3. ^ Esam El-Araby; Ivan Gonzalez; Tarek El-Ghazawi (January 2009). "Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing". ACM Transactions on Reconfigurable Technology and Systems (TRETS) 1 (4). doi:10.1145/1462586.1462590. 
  4. ^ "NSF center for High-performance Reconfigurable Computing". official web site. Retrieved August 19, 2011. 
  5. ^ "Many-Core and Reconfigurable Supercomputing Conference". official web site. 2011. Retrieved August 19, 2011.