Hybrid Memory Cube

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Hybrid Memory Cube (HMC) is a new type of computer RAM technology developed by Micron Technology. The Hybrid Memory Cube Consortium (HMCC) is backed by several major technology companies including Samsung, Micron Technology, ARM, HP, Microsoft, Altera, and Xilinx.[1]

The HMC uses 3D packaging of multiple memory dies, typically 4 or 8 memory dies per package,[2] with using of through-silicon vias (TSV) and microbumps. It has more data banks than classic DRAM memory of the same size. The Memory controller is integrated into memory package as a separate logic die.[3] The HMC uses standard DRAM cells, but its interface is incompatible with current DDRn (DDR2 or DDR3) implementations.[4]

HMC technology won the Best New Technology award from The Linley Group (publisher of Microprocessor Report magazine) in 2011.[5][6]

The First public specification, HMC 1.0, was published in April 2013.[7] According to it, The HMC uses 16-lane or 8-lane (half size) full-duplex differential serial links, with each lane having 10, 12.5 or 15 Gbit/s SerDes.[8] Each HMC package is named a cube, and they can be chained in a network of up to 8 cubes with cube-to-cube links and some cubes using their links as pass-thru links.[9] Typical cube package with 4 links has 896 BGA pins and sized 31x31x3,8 millimeters.[10]

Typical raw bandwidth of single 16-lane link with 10 Gbit/s signalling is 40 GB/s (20 GB/s transmit and 20 GB/s receive); cubes with 4 and 8 links are planned. Effective memory bandwidth utilization varies in 50%-33% for smallest packets of 32 bytes; and in 85%-45% for 128 byte packets.[2]

As reported at the HotChips 23 conference in 2011, the first generation of HMC demonstration cubes with four 50 nm DRAM memory dies and one 90 nm logic die with total capacity of 512 MB and size 27x27 mm had power consumption of 11 W and was powered with 1.2 V.[2]

Engineering samples of 2nd Generation HMC memory chips were announced in September 2013 by Micron and mass production of HMC may start in 2014.[11][12] Samples of 2GB HMC (stack of 4 memory dies, each of 4 Gbit) are packed in 31×31 mm package and has 4 HMC links. Other samples from 2013 has only two HMC links and a smaller package: 16×19.5 mm[13]

Volume production of 2 and 4 GB devices are planned for 2014.[14]

References[edit]

  1. ^ Microsoft backs Hybrid Memory Cube tech // by Gareth Halfacree, bit-tech, 9th May 2012
  2. ^ a b c Hybrid Memory Cube (HMC), J. Thomas Pawlowski (Micron) // HotChips 23
  3. ^ Micron Reinvents DRAM Memory // Linley group, Jag Bolaria, September 12, 2011
  4. ^ Memory for Exascale and ... Micron's new memory component is called HMC: Hybrid Memory Cube by Dave Resnick (Sandia National Laboratories) // 2011 Workshop on Architectures I: Exascale and Beyond, 8 July 2011
  5. ^ Micron's Hybrid Memory Cubes win tech award // by Gareth Halfacree, bit-tech, 27th January 2012
  6. ^ Best Processor Technology of 2011 // The Linley Group, Tom Halfhill, Jan 23, 2012
  7. ^ Hybrid Memory Cube receives its finished spec, promises up to 320GB per second By Jon Fingas // Engadget, Apr 3rd, 2013
  8. ^ HMC 1.0 Specification, Chapter "1 HMC Architecture"
  9. ^ HMC 1.0 Specification, Chapter "5 Chaining"
  10. ^ HMC 1.0 Specification, Chapter "19 Packages for HMC-15G-SR Devices"
  11. ^ Pete Singer (2013-07-17). "Hybrid Memory Cube nears engineering sample milestone". SolidState Technology. 
  12. ^ Tiffany Trader (2013-01-17). "Micron Readies Hybrid Memory Cube for Debut". HPCwire. 
  13. ^ Hruska, Joel (September 25, 2013). "Hybrid Memory Cube 160GB/sec RAM starts shipping: Is this the technology that finally kills DDR RAM?". Extreme Tech. Retrieved 27 September 2013. 
  14. ^ Mellor, Chris (27 November 2013). "Micron: Our STACKED SILICON BEAUTY solves the DRAM problem". www.theregister.co.uk. The Register. Retrieved 7 January 2014. 

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