I²C

File:I2clogo.jpg

I²C (Inter-Integrated Circuit) (Template:Pron-en or /ˈaɪ tuː ˈsiː/) (generically referred to as "two-wire interface") is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cellphone. Since the mid 1990s several competitors (e.g. Siemens AG (later Infineon Technologies AG), NEC, Texas Instruments, STMicroelectronics (formerly SGS-Thomson), Motorola (later Freescale), Intersil, etc.) brought I²C products on the market, which are fully compatible with the NXP (formerly Philips' semiconductor division) I²C-system. As of October 10, 2006, no licensing fees are required to implement the I²C protocol. However, fees are still required to obtain I²C slave addresses allocated by NXP.

SMBus, defined by Intel in 1995, is a subset of I²C that defines stricter electrical and protocol conventions. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I²C systems incorporate policies and rules from SMBus, sometimes supporting both I²C and SMBus with minimal re-configuration required.

Design

A sample schematic with one master (a microcontroller), three slave nodes (an ADC, a DAC, and a microcontroller), and pull-up resistors R_p

I²C uses only two bidirectional open-drain lines, Serial Data Line(SDA) and Serial Clock (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other voltages are permitted.

The I²C reference design has a 7-bit address space with 16 reserved addresses, so a maximum of 112 nodes can communicate on the same bus. Common I²C bus speeds are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode, but arbitrarily low clock frequencies are also allowed. Recent revisions of I²C can host more nodes and run faster (400 kbit/s Fast mode, 1 Mbit/s Fast mode plus or Fm+, and 3.4 Mbit/s High Speed mode); those speeds are more widely used on embedded systems than on PCs. There are other features, such as 16-bit addressing.

Note that the bit rates quoted are for the transactions between master and slave without clock stretching or other hardware overhead. Protocol overheads include a slave address and perhaps a register address within the slave device as well as per-byte ACK/NACK bits. So the actual transfer rate of user data is lower than those peak bit rates alone would imply. For example, if each interaction with a slave inefficiently allows only 1 byte of data to be transferred, the data rate will be less than half the peak bit rate.

The maximum number of nodes is limited by the address space, and also by the total bus capacitance of 400 pF, which restricts practical communication distances to a few meters.

Reference design

The reference design, as mentioned above, is a bus with a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for nodes: master and slave:

• Master node — node that issues the clock and addresses slaves
• Slave node — node that receives the clock line and address.

The bus is a multi-master bus which means any number of master nodes can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent).

There are four potential modes of operation for a given bus device, although most devices only use a single role and its two modes:

• master transmit — master node is sending data to a slave
• master receive — master node is receiving data from a slave
• slave transmit — slave node is sending data to a master
• slave receive — slave node is receiving data from the master

The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave.

If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively).

The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high.

If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.)

If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.)

The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a "combined message").

Message protocols

I²C defines three basic types of messages, each of which begins with a START and ends with a STOP:

• Single message where a master writes data to a slave;
• Single message where a master reads data from a slave;
• Combined messages, where a master issues at least two reads and/or writes to one or more slaves.

LALALALAL In a combined message, each read or write begins with a START and the slave address. After the first START, these are also called repeated START bits; repeated START bits are not preceded by STOP bits, which is how slaves know the next transfer is part of the same message.

Any given slave will only respond to particular messages, as defined by its product documentation.

Pure I²C systems support arbitrary message structures. SMBus is restricted to nine of those structures, such as read word N and write word N, involving a single slave. PMBus extends SMBus with a Group protocol, allowing multiple such SMBus transactions to be sent in one combined message. The terminating STOP indicates when those grouped actions should take effect. For example, one PMBus operation might reconfigure three power supplies (using three different I2C slave addresses), and their new configurations would take effect at the same time: when they receive that STOP.

With only a few exceptions, neither I²C nor SMBus define message semantics, such as the meaning of data bytes in messages. Message semantics are otherwise product-specific. Those exceptions include messages addressed to the I²C general call address (0x00) or to the SMBus Alert Response Address; and messages involved in the SMBus Address Resolution Protocol (ARP) for dynamic address allocation and management.

In practice, most slaves adopt request/response control models, where one or more bytes following a write command are treated as a command or address. Those bytes determine how subsequent written bytes are treated and/or how the slave responds on subsequent reads. Most SMBus operations involve single byte commands.

Messaging example: 24c32 EEPROM

One specific example is the 24c32 type EEPROM, which uses two request bytes that are called Address High and Address Low. (Accordingly, these EEPROMs aren't usable by pure SMBus hosts, which only support single byte commands or addresses.) These bytes are used to address bytes within the 32 kbit (4 kB) supported by that EEPROM; the same two byte addressing is also used by larger EEPROMs, such as 24c512 ones storing 512 kbits (64 kB). Writing and reading data to these EEPROMs uses a simple protocol: the address is written, and then data is transferred until the end of the message. (That data transfer part of the protocol also makes trouble for SMBus, since the data bytes are not preceded by a count and more than 32 bytes can be transferred at once. I2C EEPROMs smaller than 32 kbits, such as 2 kbit 24c02 ones, are often used on SMBus with inefficient single byte data transfers.)

To write to the EEPROM, a single message is used. After the START, the master sends the chip's bus address with the direction bit clear (write), then sends the two byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP. When writing multiple bytes, all the bytes must be in the same 32 byte page. While it's busy saving those bytes to memory, the EEPROM won't respond to further I2C requests. (That's another incompatibility with SMBus: SMBus devices must always respond to their bus addresses.)

To read starting at a particular address in the EEPROM, a combined message is used. After a START, the master first writes that chip's bus address with the direction bit clear (write) and then the two bytes of EEPROM data address. It then sends a (repeated) START and the EEPROM's bus address with the direction bit set (read). The EEPROM will then respond with the data bytes beginning at the specified EEPROM data address—a combined message, first a write then a read. The master issues a STOP after the first data byte it NACKs rather than ACKs (when it's read all it wants). The EEPROM increments the address after each data byte transferred; multi-byte reads can retrieve the entire contents of the EEPROM using one combined message.

Physical layer

At the physical layer, both SCL & SDA lines are of open-drain design, thus, pull-up resistors are needed. Pulling the line to ground is considered a logical zero while letting the line float is a logical one. This is used as a channel access method. High speed systems (and some others) also add a current source pull up, at least on SCL; this supports faster rise times and higher bus capacitance. Transitions for data bits are always performed while the clock is low, transitions while it is high indicate start and stop bits.

When one node is transmitting a logical one (i.e., letting the line float to Vdd) and another transmits a logical zero then the first node can sense this because the line is not in a logical one state — it is not pulled up to Vdd. When used on SCL, this is called "clock stretching" and gives slaves a flow control mechanism. When used on SDA, this is called arbitration and ensures there is only one transmitter at a time.

Clock stretching using SCL

One of the more significant features of the I²C protocol is clock stretching. An addressed slave device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master that is communicating with the slave will attempt to raise the clock to transfer the next bit, but must verify that the clock line was actually raised. If the slave is clock stretching, the clock line will still be low (because the connections are open-drain). The same is true if a second, slower, master tries to drive the clock at the same time. (If there is more than one master, all but one of them will normally lose arbitration.)

Clock stretching is not used by masters in single-master configurations. When a master wants to slow the rate of data transfer, it just delays issuing the next clock edge. Some masters, such as those found inside custom ASICs may not support clock stretching; often these devices will be labeled as a "two-wire interface" and not I²C.

To improve its robustness, SMBus places limits on how far clocks may be stretched. Hosts and slaves adhering to those limits can't block access to the bus for more than a short time, which is not a guarantee made by pure I²C systems.

Arbitration using SDA

Every master monitors the bus for start and stop bits, and does not start a message while another master is keeping the bus busy. However, two masters may start transmission at about the same time; in this case, arbitration occurs. Slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. In contrast to protocols (such as Ethernet) that use random back-off delays before issuing a retry, I²C has a deterministic arbitration policy. Each transmitter checks the level of the data line (SDA) and compares them with the levels it expects; if they don't match, that transmitter has lost arbitration, and drops out of this protocol interaction.

For example, if one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to ground), the result is that the line is low. The first transmitter then observes that the level of the line is different than expected, and concludes that another node is transmitting. The first node to notice such a difference is the one that loses arbitration: it stops driving SDA. If it's a master, it also stops driving SCL and waits for a STOP; then it may try to reissue its entire message. In the meantime, the other node has not noticed any difference between the expected and actual levels on SDA, and therefore continues transmission. It can do so without problems because so far the signal has been exactly as it expected; no other transmitter has disturbed its message.

If the two masters are sending a message to two different slaves, the one sending the lower slave address always "wins" arbitration in the address stage. Since the two masters may send messages to the same slave address—and addresses sometimes refer to multiple slaves—arbitration must continue into the data stages.

Arbitration occurs very rarely, but is necessary for proper multi-master support. As with clock-stretching, not all devices support arbitration. Those that do generally label themselves as supporting "multi-master" communication.

SMBus uses arbitration in two additional contexts, both of which are used to pass information asynchronously from slaves to the (single) host. The first context is that hosts must support the "host notify protocol". That is a restricted multi-master mode in which slaves write messages to the reserved "SMBus Host" address (0x08), passing their address and two bytes of data. When two slaves try to notify the host at the same time, one of them will lose arbitration and need to retry. The other context is that pure slave devices which issue the SMBALERT# interrupt need to arbitrate when they reply to requests issued to the reserved "SMBus Alert Response Address" (0x0c), which is a kind of broadcast address. When they successfully reply with their own address, winning an arbitration in "slave transmit" mode, they stop raising that interrupt. In both cases, arbitration applies when the slave address is transmitted.

Timing diagram

Data transfer sequence

Data transfer is initiated with the START bit (S) when SDA is pulled low while SCL stays high. Then, SDA sets the transferred bit while SCL is low (blue) and the data is sampled (received) when SCL rises (green). When the transfer is complete, a STOP bit (P) is sent by releasing the data line to allow it to be pulled up while SCL is constantly high.

Example of bit-banging the I2C Master protocol

unsigned start = 0;
unsigned read_bit(void)
{
	unsigned bit;

	/* Let the slave drive data */
	READSDA();
	I2CDELAY(I2CSPEED/2);
	/* Clock stretching */
	while (READSCL() == 0);
	/* SCL is high, now data is valid */
	bit = READSDA();
	I2CDELAY(I2CSPEED/2);
	CLRSCL();
	return bit;
}

void write_bit(unsigned bit)
{
	if (bit) {
		READSDA();
	} else {
		CLRSDA();
	}
	I2CDELAY(I2CSPEED/2);
	/* Clock stretching */
	while (READSCL() == 0);
	/* SCL is high, now data is valid */
	/* If SDA is high, check that nobody else is driving SDA */
	if (bit) {
                if (READSDA() == 0) {
		        ARBITRATION_LOST();
		}
	}
	I2CDELAY(I2CSPEED/2);
	CLRSCL();
}

void start_cond(void)
{
	if (start) {
		/* set SDA to 1 */
		READSDA();
		I2CDELAY(I2CSPEED/2);
		/* Clock stretching */
		while (READSCL() == 0);
	}
	if (READSDA() == 0) {
		ARBITRATION_LOST();
	}
	/* SCL is high, set SDA from 1 to 0 */
	CLRSDA();
	I2CDELAY(I2CSPEED/2);
	CLRSCL();
	start = 1;
}

void stop_cond(void)
{
	/* set SDA to 0 */
	CLRSDA();
	I2CDELAY(I2CSPEED/2);
	/* Clock stretching */
	while (READSCL() == 0);
	/* SCL is high, set SDA from 0 to 1 */
	if (READSDA() == 0) {
		ARBITRATION_LOST();
	}
	I2CDELAY(I2CSPEED/2);
	start = 0;
}

unsigned tx(int send_start, int send_stop, unsigned char byte)
{
	unsigned bit;
	unsigned nack;

	if (send_start) {
		start_cond();
	}
	for (bit = 0; bit < 8; bit++) {
		write_bit(byte & 0x80);
		byte <<= 1;
	}
	nack = read_bit();
	if (send_stop) {
		stop_cond();
	}
	return nack;
}

unsigned char rx (int nak, int send_stop)
{
	unsigned char byte = 0;
	unsigned bit;

	for (bit = 0; bit < 8; bit++) {
             byte <<= 1;		
             byte |= read_bit();		
	}
	write_bit(nak);
	if (send_stop) {
		stop_cond();
	}
	return byte;
}

Applications

I²C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Common applications of the I²C bus are:

• Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2 SDRAM memory sticks (DIMM) and other stacked PC boards
• Supporting systems management for PCI cards, through an SMBus 2.0 connection.
• Accessing NVRAM chips that keep user settings.
• Accessing low speed DACs and ADCs.
• Changing contrast, hue, and color balance settings in monitors (Display Data Channel).
• Changing sound volume in intelligent speakers.
• Controlling OLED/LCD displays, like in a cellphone.
• Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan speed.
• Reading real time clocks.
• Turning on and turning off the power supply of system components.

A particular strength of I²C is that a microcontroller can control a network of device chips with just two general-purpose I/O pins and software.

Peripherals can also be added to or removed from the I²C bus while the system is running, which makes it ideal for applications that require hot swapping of components.

Buses like I²C became popular when computer engineers realized that much of the manufacturing cost of an integrated circuit design results from its package size and pin count. A smaller package also usually weighs less and consumes less power, which is especially important in cellphones and portable computing. Those concerns multiply at the board level, where routing lots of signals in parallel takes up scarce space.

Operating system support

• In Microsoft Windows, I²C is implemented by the respective device drivers of much of the industry's available hardware.
• In Mac OS X, there are about two dozen I²C kernel extensions which communicate with sensors for reading voltage, current, temperature, motion, and other physical status.
• In Linux, I²C is handled with a device driver for the specific device, and another for the I²C (or SMBus) adapter to which it's connected. Several hundred such drivers are part of current releases.
• FreeBSD, NetBSD and OpenBSD also provide an I²C framework, with support for a number of common master controllers and sensors.
• In Sinclair QDOS and Minerva QL operating systems I²C is supported via a set of extensions provided by TF Services.
• In AmigaOS the shared library i2c.library by Wilhelm Noeker allows I²C access.
• eCos supports I²C for several hardware architectures.

Development tools

When developing or troubleshooting systems using I2C, visibility at the level of hardware signals can be important.

I²C host adapters

There are a number of hardware solutions for host computers, running Linux, Mac or Windows, I²C master and/or slave capabilities. Most of them are based on Universal Serial Bus (USB) to I²C adaptors. Not all of them require proprietary drivers or APIs.

I²C Host Adapters	I2C Modes	Manufacturer	Host OS / Software Supported
The 25¢ I²C Adapter	Master	Open Source	Mac, Linux (limited hardware support, see documentation)
Philips Parallel Printer Port Adaptor	Master, Multimaster, Slave	Philips Semiconductors	Linux
USB-I2C Adapter	Master	Byvac	Windows,Linux
Connii MM 2.0 I2C USB 2.0 Host Adapter	Master, Multimaster	telos	Windows, Labview
Aardvark I2C/SPI Host Adapter	Master, Multimaster, Slave	Total Phase	Linux, Windows, Mac
AnaGate I2C-Ethernet Gateway	Master, Multimaster	Analytica	Linux, Windows, PLC
The Bus Pirate	Master	Open source + Hardware	All, USB serial terminal
BusPro I2C	Master, Multimaster	Corelis	Windows
CAS-1000 I2C/SMbus Analyzer/Exerciser	Master, Multimaster, Slave	Corelis	Windows
CY3240-I2USB	Master	Cypress Semiconductor	Windows
I2C2PC Host Adaptor	Master, 3 Buses	I2CChip	All OS - simple ASCII commands
I2C-Tiny-USB	Master	Open Source + Hardware	Linux, Windows, Mac
I2C Xpress	Master, Multimaster	Byte Paradigm	Windows GUI, TCL/tk and C/C++ interfaces
iPort/USB I2C Bus Adapter	Master/Slave/Std/Fast	MCC	Windows, Linux
JI-300 I2C Bus Adapter	Master/Multi-Master	Jupiter Instruments	Windows
USB-8451	Master	National Instruments	Windows, maybe others
Tracii XL 2.0	(Multi-)Master/Slave/Tracer	telos	Windows, Labview
SUB-20 Multi Interface Adapter	Master, Multimaster, Slave	Dimax	Linux, Windows, Mac, DOS, MATLAB
U2C-12 I2C/SPI Adapter	Master	Xdimax	Linux, Windows, Mac
UCA93LV 400KHz I2C-Bus Comms Adapter	Master/Slave/Multimaster	Calibre UK Ltd	Windows
ELV USB-I2C-Interface	Master	ELV Elektronik AG	Linux, Windows, Mac, (simple ASCII-Commands)
USB-I2C	Master	Devantech	Linux, Windows, Mac, OpenBSD
USB I2C/IO Interface Board	Master, Multimaster	DeVaSys	Windows
userial USB to I2C/SPI/GPIO bridge	Master	Open Source + Hardware	Linux, Windows, Mac
TIMS-0102 USB to I2C/SPI	Master	Jova Solutions	Windows, Linux, and LabVIEW Drivers
U401/U421 USB Interface	Master	USBmicro	Linux, Windows, Mac
USB2I2C Adapter	Master	USBIO Tech	Linux, Windows and LabVIEW Drivers
ZIO	Master	Zilogic Systems	Linux. Windows

Serial to I²C bridges are also available, for systems with no USB ports.

I²C protocol analyzers

I²C Protocol Analyzers are tools which sample an I²C bus and decode the electrical signals to provide a higher-level view of the data being transmitted on the bus. The following table is sorted by manufacturer.

I²C Protocol Analyzers	Manufacturer	Price / as-of	Host Bus	Host OS, SW, API	Bus List	I²C Speeds	Notes
I²C Xpress : Analzyer and Host Adapter	Byte Paradigm	EUR 450, 2010/9	USB	Windows,Tcl/Tk,C/C++	I²C	up to 1 MHz	Host Adapter (see above)
BusPro-I : I²C Analyzer, Monitor, Debugger, Programmer	Corelis	USD 1250, 2010/9	USB HS	Windows	I²C	up to 5 MHz	.
CAS-1000-I2C/E : I²C Analyzer, Exerciser, Emulator, Programmer	Corelis	USD 7950, 2010,9	USB HS	Windows	I²C,JTAG	up to 5 MHz	Script,Scope
JI-216 : I2C Bus Monitor	Jupiter Instruments	USD 339, 2010/9	USB	Windows	I²C	up to 3.7 MHz	.
I²C/SMBus Monitor	MCC	USD 895, 2010/9	RS-232	Windows	I²C,SMBus,	up to 100 KHz	Handheld
Beagle : I²C/SPI Protocol Analyzer	Total Phase	USD 300, 2010/9	USB	Windows,Linux,Mac	I²C,SPI	up to 4 MHz	.
EasyI2C : Low Cost Protocol Analyzer	Xtreme Engineering LLC	USD 99, 2010/9	USB	Windows	I²C,TWI,SMBus	up to 400 KHz	.

Logic analyzers

When developing and/or troubleshooting the I²C bus, examination of hardware signals can be very important. Logic analyzers are tools which collect, analyze, decode, store signals so people can view the high-speed waveforms at their leisure. Logic analzyers display time-stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.

Revisions

The original I²C system was created in the early 1980s as a simple internal bus system for building control electronics with various Philips chips.

In 1992 the first standardized version was released, which added a new fast mode at 400 kbit/s and a 10-bit addressing mode to increase capacity to 1008 nodes. Version 2.0 from 1998 added high-speed mode at 3.4 Mbit/s with reduced voltage and current requirements that saved power. Version 2.1 from 2000 is a minor cleanup of version 2.0. Version 3 from 2007 adds Fast mode plus (or Fm+) and a device ID mechanism, and is the latest standard.

Limitations

The assignment of slave addresses is one weakness of I²C. Seven bits is too few to prevent address collisions between the many thousands of available devices, and manufacturers rarely dedicate enough pins to configure the full slave address used on a given board. Three pins is typical, giving only eight choices of slave address. While some devices can set multiple address bits per pin, e.g. by using a spare internal ADC channel to sense one of eight ranges set by an external voltage divider, usually each pin controls one address bit. Manufacturers may provide pins to configure a few low order bits of the address and arbitrarily set the higher order bits to some value based on the model. This limits the number of devices of that model which may be present on the same bus to some low number, typically between two and eight. That partially addresses the issue of address collisions between different vendors. Ten-bit I²C addresses are not yet widely used. [1], and many host operating systems don't support them. Neither is the complex SMBus "ARP" scheme for dynamically assigning addresses (other than for PCI cards with SMBus presence, for which it is required).

Automatic bus configuration is a related issue. A given address may be used by a number of different protocol-incompatible devices in various systems, and hardly any device types can be detected at runtime. For example 0x51 may be used by a 24LC02 or 24C32 EEPROM, with incompatible addressing; or by a PCF8563 RTC, which can't reliably be distinguished from either (without changing device state, which might not be allowed). The only reliable configuration mechanisms available to hosts involve out-of-band mechanisms such as tables provided by system firmware which list the available devices. Again, this issue can partially be addressed by ARP in SMBus systems, especially when vendor and product identifiers are used; but that hasn't really caught on. The rev 03 version of the I²C specification adds a device ID mechanism, which at this writing has not had time to catch on either.

I²C supports a limited range of speeds. Hosts supporting the multi-megabit speeds are rare. Support for the Fm+ one-megabit speed is more widespread, since its electronics are simple variants of what is used at lower speeds. Many devices don't support the 400 kbit/s speed (in part because SMBus doesn't yet support it). I²C nodes implemented in software (instead of dedicated hardware) may not even support the 100 kbit/s speed; so the whole range defined in the specification is rarely usable. All devices must at least partially support the highest speed used or they may spuriously detect their device address. Devices are allowed to stretch clock cycles to suit their particular needs, which can starve bandwidth needed by faster devices and increase latencies when talking to other device addresses. Bus capacitance also places a limit on the transfer speed, especially when current sources aren't used to decrease signal rise times.

Because of those limits (address management, bus configuration, speed), few I²C bus segments have even a dozen devices. It's common for systems to have several such segments. One might be dedicated to use with high speed devices, for low latency power management. Another might be used to control a few devices where latency and throughput aren't important issues; yet another segment might be used only to read EEPROM chips describing add-on cards (such as the SPD standard used with DRAM sticks).

Derivative technologies

I²C is the basis for the ACCESS.bus, the VESA Display Data Channel (DDC) interface, the System Management Bus (SMBus), Power Management Bus (PMBus)and the Intelligent Platform Management Bus (IPMB, one of the protocols of IPMI). These implementations have differences in voltage and clock frequency ranges, and may have interrupt lines.

TWI (Two Wire Interface) or TWSI (Two-Wire Serial Interface) is essentially the same bus implemented on various system-on-chip processors from Atmel and other vendors. Vendors use the name TWI, even though I²C is not a registered trademark. Trademark protection only exists for the respective logo (See upper right corner) and patents on I²C have now lapsed.

See also

• 1-Wire Bus
• I²S - Common for A/D and D/A converters
• Serial Peripheral Interface Bus (SPI) - Common in flash memories
• Serial Presence Detect (SPD) - Common in DRAM memories
• System Management Bus (SMB) - Common in PC motherboards
• UNI/O Bus
• List of network buses

External links

• Detailed Introduction, Primer
• Tackling I2C Development Complexities Using Innovative Tools
• Advanced I²C Bus Analysis Webinar
• What exactly is I²C?
• I²C Background
• I²C Bus / Access Bus
• Using the I²C Bus with Linux
• Proven Implementations of the I²C Bus
• OpenBSD iic(4) manual page
• Lm-sensors, Linux package which supports sensors using the I²C bus, among others.
• massmind I²C page Source code, samples and technical information for using I²C with PC, PIC and SX microcontrollers.
• Serial buses information page
• I²C Bus Technical Overview and Frequently Asked Questions
• The Bus Buffer Resource. For 2-wire buses such as I²C, SMBus, PMBus, IPMB & IPMI
• I²C Protocol
• Texas Instruments' I²C Logic Page
• A commercial hardware implementation of I²C written in VHDL
• OpenCores open source hardware implementation, in Verilog and VHDL
• Howto program the I²C protocol using the Z80 PIO
• Introduction to I²C Bus
• Introduction to SPI and I2C protocols
• I2C Protocol Decode software
• Beginner's guide to using Arduino with I²C devices, including worked examples