IA-32

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This article is about the 32-bit generation of Intel microprocessor architecture. For x86 architecture in general, see x86.

IA-32 (short for "Intel Architecture, 32-bit", sometimes also called i386[1][2] through metonymy)[3] is the third generation of the x86 architecture, first implemented in the Intel 80386 microprocessors in 1985. It was the first incarnation of x86 to support 32-bit computing.[4] As such, "IA-32" may be used as a metonym to refer to all x86 versions that support 32-bit computing.[5][6]

The IA-32 instruction set was introduced in the Intel 80386 microprocessor in 1985 and remains the basis of most PC microprocessors over twenty years later. Even though the instruction set has remained intact, the successive generations of microprocessors that run it have become much faster. Within various programming language directives, IA-32 is still sometimes referred to as the "i386" architecture.

Intel is the inventor and the biggest supplier of IA-32 processors. The second biggest supplier is AMD. As of 2013, Intel, AMD and VIA have moved to x86-64, but still produce IA-32 processors such as Intel Atom (N2xx and Z5xx series),[7] AMD Geode and the VIA C7 family. For a time, Transmeta and others, produced IA-32 processors.

Architectural features[edit]

The primary defining characteristic of IA-32 is the availability of 32-bit general-purpose processor registers (for example, EAX and EBX), 32-bit integer arithmetic and logical operations, 32-bit offsets within a segment in protected mode, and the translation of segmented addresses to 32-bit linear addresses. The designers took the opportunity to make other improvements as well. Some of the most significant changes are described below.

32-bit integer capability
All general-purpose registers (GPRs) are expanded from 16 bits to 32 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., can operate directly on 32-bit integers. Pushes and pops on the stack default to 4-byte strides, and pointers are 4 bytes wide.
More general addressing modes
Any GPR can be used as a base register, and any GPR other than ESP can be used as an index register, in a memory reference. The index register value can be multiplied by 1, 2, 4, or 8 before being added to the base register value and displacement.
Additional segment registers
Two additional segment registers, FS and GS, are provided.
Larger virtual address space
The IA-32 architecture defines a 48-bit segmented address format, with a 16-bit segment number and a 32-bit offset within the segment. Segmented addresses are mapped to 32-bit linear addresses.
Demand paging
32-bit linear addresses are virtual addresses rather than physical addresses; they are translated to physical addresses through a page table. In the 80386, 80486, and the original Pentium processors, the physical address was 32 bits; in the Pentium Pro and later processors, the Physical Address Extension allowed 36-bit physical addresses, although the linear address size was still 32 bits.

See also[edit]

References[edit]

  1. ^ "DITTO". BSD General Commands Manual. Apple. 19 December 2008. Retrieved 3 August 2013. Thin Universal binaries to the specified architecture [...] should be specified as "i386", "x86_64", etc. 
  2. ^ "Additional Predefined Macros". intel.com. Intel. Retrieved 31 August 2013. 
  3. ^ Kemp, Steve. "Running 32-bit Applications on 64-bit Debian GNU/Linux". Debian Administration. 
  4. ^ "Intel® 64 and IA-32 Architectures Software Developer's Manual". Intel Corporation. September 2014. p. 31. The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers for use both to hold operands and for addressing. 
  5. ^ Green, Ronald W. (5 May 2009). "What do IA-32, Intel 64 and IA-64 Architecture mean?". software.intel.com. Intel. Retrieved 19 December 2014. 
  6. ^ "Supported Hardware". Ubuntu Help. Canonical. Retrieved 31 August 2013. 
  7. ^ "Intel® Atom™ Processor Specifications". Intel website. Intel Corporation. Retrieved 9 December 2011.