IBM 1620 Model I

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The IBM 1620 Model I was the original implementation of the IBM 1620 scientific computer, introduced in 1959.

This unit (commonly called "1620" until the Model II was introduced) was produced as inexpensively as IBM could make it, in order to keep the price low. One industry magazine (Datamation) mentioned that the 1620 was the first IBM computer for which the basic system could be leased for a monthly rate less than its number.

It did not even have conventional ALU hardware: all arithmetic was done by table lookup in core memory. Addition and Subtraction used a 100 digit table (@ address 00300..00399). Multiplication used a 200 digit table (@ address 00100..00299). In the basic machine division used software subroutines, but optional divide hardware could be installed using a repeated subtraction algorithm. Floating point arithmetic instructions were an available option (if the divide option was installed).

IBM 1620 Model 1.jpg
IBM 1620 Model I Level H, running.
Drawing showing internal layout of "gates".

The console typewriter was a modified Model B1, which typed at only 10 characters per second. (This typewriter had a very 'nasty' habit of breaking off its "0" hammer and throwing it across the room in the middle of a long core dump. )

The first 20,000 decimal digits of core memory were internal to the CPU itself (which reduced the floor space requirements of the basic system). Expansion to either 40,000 or 60,000 decimal digits required the addition of an IBM 1623 Memory unit. The memory cycle time was 20μs ( that is, the memory speed was 50kHz = 1/20th of a MHz). A Memory Address Register Storage (MARS) Core memory read, clear, or write operation took 2 μs and each write operation was automatically (but not necessarily immediately) preceded by a read or clear operation of the same "register(s)" during the 20 μs memory cycle.

The central processor clock speed was 1 MHz, which was divided by 20 by a 10 position ring counter to provide the system timing/control signals.

Instructions took 8 memory cycles (160 μs) to fetch and a variable number of memory cycles to execute. Indirect addressing added 4 memory cycles (80 μs) for each level of indirection.

Non-decimal arithmetic[edit]

It is commonly believed that since this model used lookup tables in memory that simply changing the contents of these tables allowed the programmer to do arithmetic in any base from 2 to 10. This is only partially true as the hardware included a ten's complementer for subtraction (and addition of oppositely signed numbers). Therefore only addition of unsigned numbers could be correctly performed in bases 5 to 9. To do fully signed addition and subtraction in bases 2 to 4 required detailed understanding of the hardware to create a "folded" addition table that would fake out the complementer and carry logic. Also the addition table would have to be reloaded for normal base 10 operation every time address calculations were required in the program, then reloaded again for the alternate base. This made the "trick" somewhat less than useful for any practical application.

Operating procedures[edit]

Upper console[edit]

  • Instruction and Execute Cycle – 60 lamps
  • Control Gates – 35 lamps
  • Input-Output – 15 lamps
  • Operation Register – 25 lamps
  • Memory Buffer Register – 30 lamps
  • Memory Address Register – 25 lamps
  • Memory Address Register Display Selector – Rotary switch, 12 positions

Lower console[edit]

  • Emergency Off Pull – Pull switch
  • Check Condition status lamps/switches – 15 lamps & 5 toggle switches
  • Program Switches (sense switches) – 4 toggle switches
  • Console operator lights/switches – 13 lights, 1 power switch, and 12 buttons

Typewriter[edit]

Procedures[edit]

External links[edit]