IBM Floating Point Architecture

IBM System/360 computers, and subsequent machines based on that architecture (mainframes), support a hexadecimal floating-point format.

In comparison to IEEE 754 floating-point, the IBM floating point format has a longer significand, and a shorter exponent.

Single-precision 32 bit

A single-precision binary floating-point number is stored in a 32 bit word:

   1     7               24              width in bits
  +-+-------+------------------------+
  |S|  Exp  |   Fraction             |
  +-+-------+------------------------+
  31 30   24 23                     0    bit index (0 on right)
     bias +64

Note that in this format the initial bit is not suppressed, and the radix point is set to the left of the mantissa in increments of 4 bits.

The bias is 64 because the exponent is to the power of 16. Even though the base is 16, the exponent in this form is slightly smaller than the equivalent in IEEE 754.

An Example

Let us decode the number −118.625 using the IBM floating point system.

We need to get the sign, the exponent and the fraction.

Because it is a negative number, the sign is "1". Let's find the others.

First, we write the number (without the sign) using binary notation. Look at binary numeral system to see how to do it. The result is 1110110.101

Now, let's move the radix point left, moving four bits at a time (because IBM exponents are written to the power of 16, not 2 as in IEEE): 1110110.101=.01110110101·16²

The fraction is the part at the right of the radix point, filled with 0 on the right until we get all 24 bits. That is 011101101010000000000000.

The exponent is 2, but we need to convert it to binary and bias it (so the most negative exponent is 0, and all exponents are non-negative binary numbers). For the system/360 format, the bias is 64 and so 2 + 64 = 66. In binary, this is written as 1000010.

Putting them all together:

   1     7               24              width in bits
  +-+-------+------------------------+
  |S|  Exp  |  Fraction              |
  |1|1000010|011101101010000000000000|
  +-+-------+------------------------+
  31 30   24 23                     0    bit index (0 on right)
     bias +64

Quiet NAN (not a number)

   1     7               24              width in bits
  +-+-------+------------------------+
  |S|  Exp  |  Fraction              |
  |0|1111111|100000000000000000000000|
  +-+-------+------------------------+
  31 30   24 23                     0    bit index (0 on right)
     bias +64

• Sign bit = 0 or 1.
• Exponent = All ones.
• Fraction = Left most bit = 1 and other bit's any.

Signaling NAN (not a number)

   1     7               24              width in bits
  +-+-------+------------------------+
  |S|  Exp  |  Fraction              |
  |0|1111111|011111111111111111111111|
  +-+-------+------------------------+
  31 30   24 23                     0    bit index (0 on right)
     bias +64

• Sign bit = 0 or 1.
• Exponent = All ones.
• Fraction = Left most bit = 0 and other bit's not equal 0.

INFINITY

   1     7               24              width in bits
  +-+-------+------------------------+
  |S|  Exp  |  Fraction              |
  |0|1111111|000000000000000000000000|
  +-+-------+------------------------+
  31 30   24 23                     0    bit index (0 on right)
     bias +64

• Sign bit = 0 or 1.
• Exponent = All ones.
• Fraction = All 0.

Double-precision 64 bit

Double-precision is the same except that the mantissa (fraction) field is wider and the double-precision number is stored in a double word (8 bytes):

  1     7                               56 bits
 +-+-----------+----------------------------------------------------+
 |S|  Exp      |  Fraction                                          |
 +-+-----------+----------------------------------------------------+
 63 62       56 55                                                 0

Extended-precision 128 bit

Extended-precision (quadruple-precision) was added to the System/370 series and was available on some S/360 models (S/360-85, -195, and others by special request or simulated by OS software). The extended-precision mantissa (fraction) field is wider, and the extended-precision number is stored as two double words (16 bytes):

 High-Order Part:
  1     7                               56 bits
 +-+-----------+----------------------------------------------------+
 |S|  Exp      |  Fraction (leftmost 14 of 28 digits)               |
 +-+-----------+----------------------------------------------------+
127 126     120 119                                               64

 Low-Order Part:
        8                               56 bits
 +-------------+----------------------------------------------------+
 |   Unused    |  Fraction (rightmost 14 of 28 digits)              |
 +-------------+----------------------------------------------------+
  63         56 55                                                 0

IEEE 754 on IBM mainframes

Starting with the S/390 G5 in 1998, IBM mainframes have also included IEEE binary floating-point units which conform to the IEEE 754 Standard for Floating-Point Arithmetic. IEEE decimal floating-point was added to IBM System z9 GA2 in 2007 using millicode and in 2008 to the IBM System z10 in hardware.

Modern IBM mainframes support three floating-point radices with 3 hexadecimal (HFP) formats, 3 binary (BFP) formats, and 3 decimal (DFP) formats. There are two floating-point units per core; one supporting HFP and BFP, and one supporting DFP; note there is one register file, FPRs, which holds all 3 formats.

Special uses

The IBM floating-point format is used in:

• SAS 5 Transport files (.XPT) as required by the Food and Drug Administration (FDA) for New Drug Application (NDA) study submissions
• GRIB (GRIdded Binary) data files to exchange the output of weather prediction models,
• GDS II (Graphic Database System II) format files, and
• SEG Y (Society of Exploration Geophysicists Y) format files.

Systems which use Base-16 Excess-64 Floating Point format

• IBM System/360
• GEC 4000 series minicomputers
• Interdata 16 and 32 bit computers.

See also

• IEEE 754 Standard for Floating-Point Arithmetic
• Microsoft Binary Format

External references

• "An analysis of floating-point addition", Sweeney, D. W., IBM Systems Journal, Vol:4 Issue: 1 (1965), pp. 31–42
• "System 360 Floating-Point Problems", Tomayko, J., Anecdotes in IEEE Annals of the History of Computing, Vol:17 No:2 (Summer 1995), pp. 62–63, ISSN: 1058-6180
• Idiosyncrasies of System/360 Floating-Point, Harding, L. J., Presented at SHARE XXVII, Toronto, Canada, 1966
• Modifications of System/360 Floating Point, Harding, L. J., SHARE Secretary Distribution, SSD 157, C4470, pp. 11–27, 1966
• "The IBM System/360 Model 91: Floating-Point Execution Unit", Anderson, S. F., et al., IBM Journal of Research and Development, Vol:11 No:1 (1967), p. 34
• "Structural aspects of the system/360 model 85: III extensions to floating-point architecture", Padegs, A., IBM Systems Journal, Vol:7 No:1 (March 1968), pp. 22–29
• CMOS floating-point unit for the S/390 Parallel Enterprise Server G4, E. M. Schwarz, L. Sigal, T. J. McPherson, IBM Journal of Research and Development, Vol:41 No:4/5 (1997), p. 475