IBM System/360 Model 44
The Model 44 was announced August 16, 1965 and withdrawn September 24, 1973.
The Model 44 lacked the storage-to-storage character and decimal instruction sets of a standard System/360, however an "extended instruction set" feature was available to provide the missing instructions. The machine featured four unique instructions: Chanqe Priority Mask (CHPM), Load PSW Special (LPSX), Read Direct Word (RDDW), and Write Direct Word (WRDW).:p.73
The system came with four memory sizes: E (32 KiB), F (64 KiB), G (128 KiB), and H (256 KiB), with an access time of 1 μs, which put it closer to the Model 65 (.75 μs) than the Model 50 (2.0 μs).:pp.6-11,6-12 Storage protection was an optional feature.:p.9
General purpose registers were normally located in a non-addressable portion of 1 μs core storage termed "bump storage". For added speed, the general purpose registers could be implemented in Solid Logic Technology (SLT) circuitry with an access time of .25 μs.:p.8
A unique feature of the Model 44 was "variable-length precision floating point arithmetic". It had the same short floating-point instructions and long floating-point instructions as the other models in the System/360 line, but it also had a rotary switch on the front panel which could be used to set the precision of long floating-point numbers. The mantissa portion of long floating-point numbers could be chosen as 32, 40, 48, or 56 bits, with 56 bits being the standard value. Whatever the setting, long floating-point numbers still occupied 64 bits in memory (the first eight bits were the sign and the exponent); the setting only led, when it was less than 56 bits, to long floating-point operations ignoring some of the least significant bits of these numbers. This provided an improvement in speed when greater precision was not needed.:p.13
An optional feature provided six external interrupt lines.:p.9
The direct word feature allowed the transfer of a full 32-bit word of information between an external device and main storage. This differed from the standard System/360 direct control feature which transferred a single byte. The Write Direct Word instruction placed the contents of a word in memory as static signals on the 32 direct-out lines and used the I2 field of the instruction as up to eight timing pulses. The Read Direct Word read the 32 direct-in lines into memory and sent the I2 field as timing pulses.:p.5
Write Direct Word ('B4'x): WRDW D1(B1),I2
Read Direct Word ('B5'x): RDDW D1(B1),I2
The direct data channel feature provided a fast, simple data transfer capability. Controlled by standard System/360 I/O instructions and commands, it allowed the connection of external devices that performed word-by-word data transfers with the Model 44 CPU at transfer rates up to 4 MiB/s.:pp.12-16
The priority interrupt feature added thirty-two interrupt levels to the standard five. This used locations '800'x to '9FF'x for the old and new program status word locations. An eight bit interrupt description from the interrupting device was stored in bit positions 24 to 31 of the corresponding old PSW. Bits 16-23 of the new PSW were used as a mask which was XORed with the interrupt description to modify the address from the new PSW, effectively allowing indexing into a jump table for the interrupt according to data sent by the device. The interrupts were numbered from 0 (highest priority) to 31 (lowest); a higher priority interrupt could interrupt processing of a lower priority. A 32 bit Priority Mask Register, set by the Change Priority Mask instruction, could be used to selectively mask interrupts to keep them in pending status until the mask was reset. The instruction could enable levels tagged by 1 bits, disable levels tagged by 0 bits cancel levels tagged by 1 bits, or cancel and enable levels tagged by 1 bits depending on the value of the I2 field. The Load PSW Special instruction was used to exit an interrupt routine resume the next highest priority routine or non-interrupt code.:pp.17-21
Load PSW Special ('B2'x): LPSX D1(B1),I2
I2 was reserved and should be zero.
Change Priority Mask ('B3'x): CHPM D1(B1),I2
The high order two bits of the I2 field were called the mask bit and the cancel bit.
The remainder of the I2 field was reserved and should be zero.
(mask bit) (cancel bit) Function 1 0 Enable levels tagged by 1 bits 0 0 Disable levels tagged by 0 bits 0 1 Cancel levels tagged by 1 bits 1 1 Cancel and enable levels tagged by 1 bits
The Model 44 could support up to one standard and two high-speed System/360 multiplexer channels in addition to integrated adapters for the single disk storage and the console 1052 printer/keyboard.
A unique feature of the Model 44 was its integrated single disk storage drive which used the IBM 2315 cartridge and provided approximately 1 MiB of removable disk storage built right into the CPU. A second integrated drive was available as an option.:p.12 The Model 44 Programming System (M44PS) used this drive as a systems residence device.:p.7
- IBM Corporation. "IBM Archives: System/360 Model 44". Retrieved October 18, 2012.
- IBM Corporation (1966). IBM System/360 Model 44 Programming System Assembler Language.
- IBM Corporation (1974). IBM System/360 System Summary.
- IBM Corporation. IBM System/360 Model 44 Functional Characteristics.
- IBM Corporation. Data Acquisition Special Features for the IBM System/360 Model 44.
- IBM Corporation (1966). IBM System/360 Model 44 Programming System Concepts and Facilities.