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Modern microprocessors are much faster than the memory where the program is kept, meaning that the program's instructions cannot be read fast enough to keep the microprocessor busy. Adding a cache can provide faster access to needed instructions.
Prefetching occurs when a processor requests an instruction from main memory before it is actually needed. Once the instruction comes back from memory, it is placed in a cache. When an instruction is actually needed, the instruction can be accessed much more quickly from the cache than if it had to make a request from memory.
Since programs are generally executed sequentially, performance is likely to be best when instructions are prefetched in program order. Alternatively, the prefetch may be part of a complex branch prediction algorithm, where the processor tries to anticipate the result of a calculation and fetch the right instructions in advance. In the case of dedicated hardware (like a Graphics Processing Unit) the prefetch can take advantage of the spatial coherence usually found in the texture mapping process. In this case, the prefetched data are not instructions, but texture elements (texels) that are candidates to be mapped on a polygon.
- Halstead, Robert; Ward, Stephen (1989). Computation Structures. MIT Press. p. 812. ISBN 0-262-23139-5.
- David Callahan, Ken Kennedy, Allan Porterfield (April 1991). "Software prefetching". 4th Conference on Architectural Support of Programming Languages & Operating Systems. New York, NY, USA: ACM. pp. 40–52. doi:10.1145/106972.106979. ISBN 0-89791-380-9. Retrieved 2010-11-21.
- Chi-Keung Luk, Todd C. Mowry (October 1996). "Compiler-based prefetching for recursive data structures". 7th Conference on Architectural Support of Programming Languages & Operating Systems. New York, NY, USA: ACM. pp. 222–233. doi:10.1145/237090.237190. ISBN 0-89791-767-7. Retrieved 2010-11-21.
- Abdel-Hameed Badawy, Aneesh Aggarwal, Donald Yeung, Chau-Wen Tseng (July 2004). "The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems". The Journal of Instruction-Level Parallelism 6. ISSN 1942-9525.
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