Intel 8008
 An Intel 8008 Microprocessor | |
| General information | |
|---|---|
| Launched | mid 1972 |
| Discontinued | 1983[1] |
| Common manufacturer(s) |
|
| Performance | |
| Max. CPU clock rate | 0.5 Mhz to 0.8 Mhz |
| Architecture and classification | |
| Instruction set | pre x86 |
| Physical specifications | |
| Package(s) |
|
The Intel 8008 was an early byte-oriented microprocessor designed and manufactured by Intel and introduced in April 1972. Originally codenamed 1201, the chip was commissioned by Computer Terminal Corporation to implement an instruction set designed for their Datapoint 2200 programmable terminal. As the chip was delayed and did not meet CTC's performance goals, the 2200 ended up using CTC's own TTL based CPU instead, however, an agreement permitted Intel to market the chip to other customers.
Implemented in 10 μm silicon-gate enhancement load PMOS, initial versions of the 8008 ran at 0.5 MHz, later increased in the 8008-1 to 0.8 MHz. Instructions took between 3 and 11 cycles: register-register loads and ALU operations took 5T (10μs at 0.5 MHz), register-memory 8T (16μs), while (taken) calls and jumps took 11 cycles (22μs). The 8008 was a little slower in terms of instructions per second (45,000 to 100,000) [1] than the 4-bit Intel 4004 and Intel 4040, but the fact that the 8008 processed data eight bits at a time and could access significantly more RAM still gave it a significant speed advantage in most applications. The 8008 had 3,500 transistors[2].
The subsequent Intel 8080 and 8085 CPUs were also heavily based on the same basic design; even the x86 architecture (originally a non-strict extension of the 8085) loosely resembles the original Datapoint 2200 design (every instruction of the 8008's instruction set has a direct equivalent in the 8080's larger instruction set and Intel Core 2's even larger instruction set, although the opcode values are different in all three).
The chip (limited by its 18 pin DIP packaging) had a single 8-bit bus and required a significant amount of external support logic. For example, the 14-bit address, which could access "16 K x 8 bits of memory"[3], needed to be latched by some of this logic into an external Memory Address Register (MAR). The 8008 could access 8 input ports and 24 output ports.
For controller and CRT terminal use this was an acceptable design, but it was too difficult to use for most other tasks. A few early computer designs were based on it, but most would use the later and greatly improved Intel 8080 instead.
The 8008 family is also referred to as the MCS-8.
Designers
- CTC (Instruction set and architecture): Victor Poor and Harry Pyle.
- Intel (Implementation in silicon):
- Marcian "Ted" Hoff and Stan Mazor and Larry Potter (IBM Chief Scientist of IBM) proposed a single-chip implementation of the CTC architecture, using RAM register memory rather than shift register memory, and also added a few instructions and interrupt facility
- Federico Faggin become leader of the project from January 1971, after it had been suspended -without progress- for about 7 months, until its successful completion in April 1972
- Hal Feeney project engineer did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology Faggin originally developed for the Intel 4004 microprocessor and utilizing the circuits of the 4004.
External links
- MCS-8 User Manual with 8008 data sheet (1972)
References
- ^ CPU History - The CPU Museum - Life Cycle of the CPU
- ^ Reichel-Orbital museum - CPU Collection
- ^ MCS-8 User Manual "MCS-8 Users Manual" (pdf).
{{cite web}}: Check|url=value (help)