Intel Core (microarchitecture)

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The Intel Core microarchitecture (previously known as the Intel Next-Generation Micro-Architecture, or NGMA) is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. It is based around an updated version of the Yonah core and could be considered the latest iteration of the Intel P6 microarchitecture, which traces its history back to the 1995 Pentium Pro. The extreme power consumption of NetBurst-based processors and the resulting inability to effectively increase clock speed was the primary reason Intel abandoned the NetBurst architecture. The Intel Core Microarchitecture was designed by the Intel Israel (IDC) team that previously designed the Pentium M mobile processor.

The architecture features lower power usage than before and is competitive with AMD in heat production.^{[citation needed]} It has multiple cores and hardware virtualization support (marketed as Intel VT), as well as Intel 64 and SSSE3.

The first processors that used this architecture were code-named Merom, Conroe, and Woodcrest; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. Mainstream Core-based processors are branded Pentium Dual Core and low end branded Celeron; server and workstation Core-based processors are branded Xeon, while desktop and mobile Core-based processors are branded as Core 2. Despite their name, processors sold as Intel Core do not actually use the Core microarchitecture.

Intel CPU core roadmaps from NetBurst and Pentium M to Sandy Bridge. The Core family of processors are those with the light green background.

[edit] Technology

Intel Core 2 microarchitecture.

The Intel Core Microarchitecture is designed from the ground up, but similar to the Pentium M microarchitecture in design philosophy. The pipeline is 14 stages long — less than half of Prescott's, a signature feature of wide order execution cores. Core's execution unit is 4 issues wide, compared to the 3-issue cores of P6, P-M (Banias, Dothan, and Yonah), and NetBurst microarchitectures. The new architecture is a dual core design with linked L1 cache and shared L2 cache engineered for maximum performance per watt and improved scalability.

One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single micro-operation. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op.

Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, ramping up speed dynamically as needed (similar to AMD's Cool'n'Quiet power-saving technology, as well as Intel's own SpeedStep technology from earlier mobile processors). This allows the chip to produce less heat, and consume as little power as possible.

For most Woodcrest CPUs, the front side bus (FSB) runs at 1333 MT/s; however, this is scaled down to 1066 MT/s for lower end 1.60 and 1.86 GHz variants.^[1][2] The Merom mobile variant was initially targeted to run at a FSB of 667 MT/s while the second wave of Meroms, supporting 800 MT/s FSB, were released as part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800 MT/s or 1066 MT/s with a 1333 MT/s line officially launched on July 22, 2007.

In 2007, AMD released a series of videos claiming that the FSB will prove to be the weak link for Intel, as the Core microarchitecture uses a shared bus, unlike their own HyperTransport.^{[citation needed]} While not so critical in the mobile and desktop segments, this might be the handicap which will prevent Woodcrest-MP from taking the performance lead from AMD Opteron on systems with more than 2 cores per socket. Intel attempted to alleviate this problem by the use of advanced prefetchers and memory disambiguation which try to hide main-memory-access latency. However, this is mitigated to some degree by the use of a separate front-side bus for each physical CPU package.

The power consumption of these new processors is extremely low—average use energy consumption is to be in the 1-2 watt range in ultra low voltage variants, with thermal design powers (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0 GHz Woodcrest, and 40 watts for the low-voltage Woodcrest. However, this is subject to change. In comparison, an AMD Opteron 875HE processor consumes 55 watts, while the new Energy Efficient Socket AM2 line fits in the 35 watt thermal envelope (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for Ultra Low Voltage (ULV) versions.

Previously, Intel warned that it would now focus on power efficiency, rather than raw performance. However, at IDF in the spring of 2006, Intel advertised both. Some of the promised numbers are:

• 20% more performance for Merom at the same power level (compared to Core Duo)
• 40% more performance for Conroe at 40% less power (compared to Pentium D)
• 80% more performance for Woodcrest at 35% less power (compared to the original dual-core Xeon)

[edit] Steppings

The Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only represent incremental improvements but also different sets of features like cache size and low power modes. Most of these steppings are used across brands, typically by disabling some of the features and limiting clock frequencies on low-end chips.

Steppings with a reduced cache size use a separate naming scheme, which means that the releases are no longer in alphabetic order. Additional steppings have been used in internal and engineering samples, but are not listed in the tables.

Many of the high-end Core 2 and Xeon processors use Multi-Chip Modules of two or three chips in order to get larger cache sizes or more than two cores.

[edit] Steppings using 65 nm process

Steppings B2/B3, E1 and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard Merom/Conroe die with 4 MiB L2 cache, with the short-lived E1 stepping only being used in mobile processors. Stepping L2 and M0 are the "Allendale" chips with just 2 MiB L2 cache, reducing production cost and power consumption for low-end processors.

The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktop processors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0 add support for the Mobile Intel 965 Express (Santa Rosa) platform with Socket P, while the earlier B2 and L2 steppings only appear for the Socket M based Mobile Intel 945 Express (Napa refresh) platform.

The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and 1 MiB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.

Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was introduced to replace the original stepping B2^[3].

[edit] Steppings using 45 nm process

In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.

In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express chipsets with the Montavina platform.

Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².^[4] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).

[edit] Current processors

[edit] Laptops

[edit] Desktops

[edit] Servers and workstations

[edit] Future processors

[edit] Laptops

[edit] Servers and workstations

[edit] See also

• x86 architecture
• x86-64
• P5
• P6
• NetBurst
• Nehalem
• Sandy Bridge
• List of Intel CPU microarchitectures
• Intel Core 2
• List of Intel microprocessors
• List of Intel Celeron microprocessors
• List of future Intel Celeron microprocessors
• List of Intel Pentium Dual-Core microprocessors
• List of Intel Core 2 microprocessors
• List of future Intel Core 2 microprocessors
• List of Intel Xeon microprocessors
• List of future Intel Xeon microprocessors

[edit] References

• Intel Core Microarchitecture website
• Intel press release announcing plans for a new microarchitecture
• Intel press release introducing the Core Microarchitecture
• Intel processor roadmap
• A Detailed Look at Intel's New Core Architecture
• Intel names the Core Microarchitecture
• Pictures of processors using the Core Microarchitecture, among others (also first mention of Clovertown-MP)
• IDF keynotes, advertising the performance of the new processors
• The Core of Intel's new chips
• RealWorld Tech's overview of the Core microarchitecture
• Detailed overview of the Core microarchitecture at Ars Technica
• Intel Core versus AMD's K8 architecture at Anandtech
• Release dates of upcoming Intel Core processors using the Intel Core Microarchitecture
• Benchmarks Comparing the Computational Power of Core Architeture against Older Intel Netburst and AMD Athlon64 Central Processing Units